iCE40LP384-SG48 - 384 LUT Ultra-Low-Power FPGA | Lattice Semi
MPN: iCE40LP384-SG48 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3.95 | $3.95 |
| 10 | $3.55 | $35.50 |
| 100 | $3.1 | $310.00 |
| 500 | $2.75 | $1,375.00 |
| 1,000 | $2.45 | $2,450.00 |
| 3,000 | $2.1 | $6,300.00 |
iCE40LP384-SG48 Overview
An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit composed of configurable logic blocks (LUTs), programmable interconnect, and I/O cells that can be re-programmed to implement arbitrary digital logic. Low-power FPGAs such as the iCE40 LP family occupy a unique tier in the programmable logic hierarchy - sitting above fixed-function ASICs (which offer zero flexibility) and below high-density FPGAs from Xilinx and Intel (which offer millions of LUTs at the cost of watts). The iCE40 LP family is the de-facto choice when an application needs custom logic, multiple interfaces, or hardware acceleration, but the system can only afford a few hundred microwatts of quiescent draw. Within the Lattice portfolio, iCE40LP sits between the older iCE65 and the higher-density ECP5 family.
Key features include 384 4-input LUTs, 21 user I/O pins, embedded RAM (4 kbits block RAM equivalent), two 16-bit timers/counters, two I2C controllers, one SPI controller, and a hard PLL supporting clock multiplication. The device operates from a 1.14 V to 1.26 V core supply with separate I/O bank supplies from 1.71 V to 3.465 V, enabling direct interfacing to 1.8 V, 2.5 V, and 3.3 V peripherals. Typical static current is below 100 uA at 25 C, and active current scales linearly with toggle rate and logic utilization.
Architecturally, the iCE40LP384 uses a non-volatile SRAM configuration cell (volatile SRAM, but loaded from NV memory at boot) backed by NVCM or SPI Flash. Logic is implemented as 4-input LUTs feeding a programmable interconnect fabric, with carry chains for arithmetic and block RAM for storage. The hard I2C and SPI controllers reduce LUT usage for common bus interfaces, leaving more logic free for application-specific state machines and datapaths.
Typical applications include mobile device glue logic, IoT sensor hubs, wearable sensor aggregation, low-power display controllers (SPI/parallel LCD), handheld medical peripherals, and battery-powered industrial sensor nodes. The 48-pin QFN package balances I/O count with hand-solder-friendly footprint for prototype work.
When designing with this device, remember that the 1.2 V core rail must be sequenced within 50 ms of the I/O rails to prevent I/O cell back-powering through ESD diodes. Use the Lattice iCEcube2 design suite for synthesis, place-and-route, and bitstream generation.
Drop-in alternatives for iCE40LP384-SG48 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
iCE40LP1K-SG48
✅ Drop-In📋 Reference alternative (not in catalog)
iCE40LP384-SG48TR
✅ Drop-In📋 Reference alternative (not in catalog)
iCE40LP384-SG48-CAL
✅ Drop-In📋 Reference alternative (not in catalog)
iCE40LP384-CB48
✅ Drop-In📋 Reference alternative (not in catalog)
iCE5LP4K-SG48
✅ Drop-In📋 Reference alternative (not in catalog)
iCE40LP384-SG48 Maximum Ratings & Electrical Characteristics
| Family | iCE40 LP |
| Logic Cells (LUTs) | 384 |
| Package | 48-pin QFN (SG48) |
| User I/O | 21 |
| Core Voltage | 1.14 V to 1.26 V (typ. 1.2 V) |
| I/O Bank Voltage | 1.71 V to 3.465 V |
| Process Technology | 40 nm CMOS |
| Configuration Interface | SPI (master/slave), NVCM |
| Hard I2C Controllers | 2 |
| Hard SPI Controllers | 1 |
| PLL Blocks | 1 (hard PLL) |
| Static Current (typical) | <100 uA at 25 C |
| Operating Temperature | -40C to +85C (industrial) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead-Free | Yes |
iCE40LP384-SG48 Pin Configuration
| Pin 1 | IOB_0 — User I/O bank B, pin 0 |
| Pin 2 | IOB_1 — User I/O bank B, pin 1 |
| Pin 3 | IOB_2 — User I/O bank B, pin 2 |
| Pin 4 | IOB_3 — User I/O bank B, pin 3 |
| Pin 5 | IOB_4 — User I/O bank B, pin 4 |
| Pin 6 | GND — Ground reference |
| Pin 7 | VCCIO_0 — I/O bank 0 supply (1.71 V to 3.465 V) |
| Pin 8 | IOB_5 — User I/O bank B, pin 5 |
| Pin 9 | IOB_6 — User I/O bank B, pin 6 |
| Pin 10 | IOB_7 — User I/O bank B, pin 7 |
| Pin 11 | IOB_8 — User I/O bank B, pin 8 |
| Pin 12 | VCC — Core supply (1.2 V nominal) |
| Pin 13 | IOB_9 — User I/O bank B, pin 9 |
| Pin 14 | IOB_10 — User I/O bank B, pin 10 |
| Pin 15 | GND — Ground reference |
| Pin 16 | IOB_11 — User I/O bank B, pin 11 |
| Pin 17 | IOB_12 — User I/O bank B, pin 12 |
| Pin 18 | IOB_13 — User I/O bank B, pin 13 |
| Pin 19 | CDONE — Configuration done indicator (open-drain) |
| Pin 20 | CRESET_B — Configuration reset (active low) |
| Pin 21 | IOB_14 — User I/O bank B, pin 14 |
| Pin 22 | IOB_15 — User I/O bank B, pin 15 |
| Pin 23 | IOB_16 — User I/O bank B, pin 16 |
| Pin 24 | IOB_17 — User I/O bank B, pin 17 |
| Pin 25 | IOB_18 — User I/O bank B, pin 18 |
| Pin 26 | IOB_19 — User I/O bank B, pin 19 |
| Pin 27 | IOB_20 — User I/O bank B, pin 20 |
| Pin 28 | GND — Ground reference |
| Pin 29 | VCCIO_1 — I/O bank 1 supply (1.71 V to 3.465 V) |
| Pin 30 | IOA_0 — User I/O bank A, pin 0 |
| Pin 31 | IOA_1 — User I/O bank A, pin 1 |
| Pin 32 | IOA_2 — User I/O bank A, pin 2 |
| Pin 33 | IOA_3 — User I/O bank A, pin 3 |
| Pin 34 | IOA_4 — User I/O bank A, pin 4 |
| Pin 35 | IOA_5 — User I/O bank A, pin 5 |
| Pin 36 | VCC — Core supply (1.2 V nominal) |
| Pin 37 | IOA_6 — User I/O bank A, pin 6 |
| Pin 38 | IOA_7 — User I/O bank A, pin 7 |
| Pin 39 | IOA_8 — User I/O bank A, pin 8 |
| Pin 40 | GND — Ground reference |
| Pin 41 | IOA_9 — User I/O bank A, pin 9 |
| Pin 42 | IOA_10 — User I/O bank A, pin 10 |
| Pin 43 | IOA_11 — User I/O bank A, pin 11 |
| Pin 44 | IOA_12 — User I/O bank A, pin 12 |
| Pin 45 | IOA_13 — User I/O bank A, pin 13 |
| Pin 46 | CB_SPI_SO — Configuration SPI serial output |
| Pin 47 | CB_SPI_SI — Configuration SPI serial input |
| Pin 48 | CB_SPI_SCK — Configuration SPI serial clock |
| Pin EP | EP — Exposed thermal pad - connect to GND |
Typical Applications
iCE40LP384-SG48 is suitable for 6 applications: Mobile Device Glue Logic, Wearable Sensor Aggregation, IoT Sensor Hubs, Low-Power Display Controllers (SPI/Parallel LCD), Handheld Medical Peripherals, Battery-Powered Industrial Sensor Nodes.
Mobile Device Glue Logic
The iCE40LP384-SG48 fits mobile device glue-logic roles because its 384 LUTs, 21 I/Os, and sub-100 uA static current allow it to bridge sensors, displays, and application processors without taxing the battery budget. With the iCE40 LP family's 1.2 V core and integrated I2C/SPI controllers, it can run as a side-channel multiplexer, keypad scanner, or haptics-pattern generator next to a smartphone SoC. The 48-pin QFN reflows cleanly on the main phone PCB and adds under 10 mm^2 of board area.
Recommended
Wearable Sensor Aggregation
For wearable sensor aggregation, the iCE40LP384-SG48's ultra-low active power and tiny QFN footprint make it ideal as a pre-processor that fuses accelerometer, optical heart-rate, and temperature data before passing a compact packet to a BLE radio. The two hard I2C controllers handle up to two sensor buses natively, and the PLL multiplies a low-frequency 32.768 kHz crystal for periodic sampling without a separate clock generator. Sub-mW average draw preserves multi-day battery life on coin cells.
Recommended
IoT Sensor Hubs
The iCE40LP384-SG48 suits IoT sensor hubs that aggregate multiple low-speed peripheral buses (I2C, SPI, UART) and present a unified interface to an upstream Cortex-M0/M4 host. With 21 user I/Os, you can route up to three I2C buses, two SPI slaves, and a few GPIOs simultaneously. The 1.2 V core and 40 nm CMOS process keep quiescent draw under 100 uA - ideal for energy-harvested nodes running on a small solar cell or thermal gradient.
Recommended
Low-Power Display Controllers (SPI/Parallel LCD)
Driving a small SPI or parallel TFT-LCD from a low-power MCU is a perfect fit for the iCE40LP384-SG48, where its 384 LUTs handle pixel timing, partial-frame buffer, and gamma correction while the host MCU sleeps. The 21 user I/Os support 8-bit parallel LCD data plus control signals, and the hard SPI controller provides a clean high-speed interface to upstream hosts. Active power stays in the low mA range even at 30 Hz full-screen refresh rates.
Recommended
Handheld Medical Peripherals
In handheld medical peripherals such as pulse-oximeter dongles, glucose-meter add-on modules, and connected thermometers, the iCE40LP384-SG48 provides the bridge between sensor front-ends and BLE radios while drawing under 100 uA static. The hard I2C cores talk to optical and temperature sensors natively, and the 1.2 V core tolerates Li-coin or rechargeable Li-Ion operation with simple LDO regulation. Its small 48-pin QFN footprint fits inside fingertip-sized enclosures.
Recommended
Battery-Powered Industrial Sensor Nodes
The iCE40LP384-SG48 fits battery-powered industrial sensor nodes where Modbus, IO-Link, or 4-20 mA loop translation is required and operating life on a single D-cell must exceed five years. Its sub-100 uA static current and <1 mA active draw preserve battery, while the 21 I/Os handle multiple digital inputs plus an RS-485 transceiver interface. The 48-pin QFN's exposed thermal pad supports operation across -40 C to +85 C industrial temperature ranges.
Recommended
Recommended Products Summary
Engineering reference data for iCE40LP384-SG48 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | iCE40LP1K-SG48 | iCE40LP384-SG48TR | iCE40LP384-SG48-CAL | iCE40LP384-CB48 | iCE5LP4K-SG48 |
|---|---|---|---|---|---|---|
| Brand | Lattice Semiconductor | Lattice Semiconductor | Lattice Semiconductor | Lattice Semiconductor | Lattice Semiconductor | Lattice Semiconductor |
| Package | 48-pin QFN (SG48) | 48-pin QFN (SG48) - same | 48-pin QFN (SG48) - same | 48-pin QFN (SG48) - same | 48-ball ucBGA (CB48) - different footprint | 48-pin QFN (SG48) - same |
| Logic Cells (LUTs) | 384 | 1280 (+233%) | 384 (identical) | 384 (identical) | 384 (identical) | 3520 (+817%) |
| Core Voltage | 1.2 V (1.14-1.26 V) | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
| Hard I2C Controllers | 2 | 2 | 2 | 2 | 2 | 2 |
| Static Current (typ) | <100 uA | <100 uA | <100 uA | <100 uA | <100 uA | <100 uA |
| Process Technology | 40 nm CMOS | 40 nm CMOS | 40 nm CMOS | 40 nm CMOS | 40 nm CMOS | 40 nm CMOS |
Key Differentiators
- Lowest static power in its class (vs Lattice MachXO2-256 (LCMXO2-256HC-4SG32I))
- Hard I2C controllers free LUTs for application logic (vs iCE40LP384-CB48 (48-ball ucBGA))
- Firmware-compatible upgrade path within same family (vs iCE40LP1K-SG48)
Design Notes
Estimated: the iCE40LP384 draws under 100 uA static at 25 C on the 1.2 V core, but peak active current during configuration can briefly hit 5-10 mA. Place a 1 uF X7R ceramic bypass capacitor on VCC within 5 mm of the pin, and a second 100 nF X7R in parallel. The I/O bank supplies (VCCIO_0 and VCCIO_1) each need their own 100 nF decoupling capacitor. Per Lattice TN1288, the 1.2 V core rail must rise within 50 ms of the I/O rails; failure to meet this can cause I/O back-powering through ESD diodes and shorten device lifetime.
The SG48 package's exposed thermal pad (EP) on the bottom of the QFN is the primary heat-dissipation path and the ground reference. Solder the EP to a continuous ground plane with at least 8 thermal vias (0.3 mm drill, 0.5 mm pitch) for reliable operation. Missing the EP solder connection is the most common cause of configuration failure on this family. Per the Lattice iCE40LP datasheet, the SG48 PCB footprint should follow JEDEC MO-220 with a 0.4 mm pitch and 0.2 mm pad-to-mask clearance.
Route the configuration SPI signals (CB_SPI_SCK, CB_SPI_SI, CB_SPI_SO) as a short daisy-chain with 50-ohm characteristic impedance and ground reference on the layer beneath. Keep CRESET_B and CDONE traces short and away from high-frequency switching I/O to avoid false configuration triggers. Per Lattice TN1279 (iCE40 Hardware Checklist), the SPI configuration flash should sit within 25 mm of the FPGA and share the same ground reference, with a 10 kohm pull-up on CRESET_B to VCCIO_1.
Three common pitfalls: (1) Driving user I/O before VCCIO has reached its minimum 1.71 V threshold - this causes contention and high current draw; gate any external driver until CDONE goes high. (2) Forgetting to power down unused I/O banks - tie unused VCCIO pins to a valid 1.8 V or 3.3 V rail, never leave them floating. (3) Using the wrong iCEcube2 bitstream mode - confirm the bitstream was generated for iCE40LP384 (not iCE5LP or iCE40HX) by checking the 'family' field in the .hex file header before programming.
Compliance Information
RoHS and REACH compliance per Lattice product page. Not AEC-Q100 qualified - Lattice does not market the iCE40LP family as automotive grade. Halogen-free status not explicitly stated in the verified data.
