IPT026N10N5ATMA1 - 100V 2.6mΩ OptiMOS 5 MOSFET TOLL | Infineon
MPN: IPT026N10N5ATMA1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2.95 | $2.95 |
| 10 | $2.66 | $26.60 |
| 100 | $2.36 | $236.00 |
| 500 | $2.1 | $1,050.00 |
| 1,000 | $1.87 | $1,870.00 |
IPT026N10N5ATMA1 Overview
An N-channel power MOSFET is a voltage-controlled majority-carrier device in which a positive gate-source bias inverts the surface of a P-region, forming an N-channel that conducts current between drain and source. Modern trench MOSFETs such as OptiMOS 5 push cell density higher than planar generations, which simultaneously reduces on-resistance per unit area and lowers gate charge. In the broader taxonomy, the IPT026N10N5ATMA1 sits inside power MOSFETs > MOSFETs > transistors > discrete semiconductors, occupying the low-voltage high-current corner of that hierarchy.
Key differentiating parameters include the 2.6 mΩ maximum RDS(on) at VGS=10 V, the sub-100 ns turn-on/turn-off transition enabled by low Qg and Qgd figures, and the small TOLL outline which shrinks the footprint by roughly 60 % versus D2PAK while doubling power density. The integrated source-connected tab improves PCB thermal spreading and allows the part to be cooled primarily through the PCB copper rather than an external heatsink at moderate loads.
Architecturally, the OptiMOS 5 platform combines a fine-pitch trench gate with a shielded-cell layout to balance dv/dt ruggedness against body-diode reverse recovery. Compared to older OptiMOS 3/4 generations in the same voltage class, the IPT026N10N5 typically achieves a 30-40 % lower figure of merit (RDS(on) × Qg) which directly translates into cooler operation at high switching frequencies.
Typical applications include synchronous rectification in 48 V server and telecom DC-DC converters, brushless DC motor drives for industrial fans and pumps, hot-swap and OR-ing switches on telecom boards, solar micro-inverters, and Class-D audio output stages where low conduction loss reduces thermal stress on the heatsink.
When designing with this part, ensure that gate-drive voltage reaches at least 10 V for full enhancement, and place the gate resistor close to the gate pin to suppress parasitic ringing. For high di/dt loops, keep the source-return path as short as possible and use a Kelvin-source footprint if available on the PCB pad pattern.
This page synthesizes distributor pricing, pin-compatible alternatives in the same TOLL/HSOF-8-1 footprint, and practical design notes not aggregated in the manufacturer datasheet.
Drop-in alternatives for IPT026N10N5ATMA1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with IPT026N10N5ATMA1 (same form factor and footprint) — differing in Technology, Package, Configuration, Operating Temperature Range, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
IPT015N10N5ATMA1
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IPT027N10N5ATMA1
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BSC076N04NDATMA1
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View Datasheet →IPC100N04S5L1R5ATMA1
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View Datasheet →IPT026N10N5ATMA1 Maximum Ratings & Electrical Characteristics
| Manufacturer | Infineon Technologies |
| Product Family | OptiMOS 5 |
| Transistor Type | N-Channel MOSFET |
| Drain-Source Voltage (VDS) | 100 V |
| Gate-Source Voltage (VGS) | ±20 V |
| Continuous Drain Current (ID, Tc=25°C) | 202 A |
| Continuous Drain Current (ID, Ta) | 27 A |
| Maximum RDS(on) at VGS=10V | 2.6 mΩ |
| Maximum Power Dissipation (Tc=25°C) | 214 W |
| Package | PG-HSOF-8-1 (TOLL) |
| Mounting Type | Surface Mount |
| Operating Temperature Range | -55 °C to +175 °C (TJ) |
| Configuration | Single with built-in diode |
| Number of Terminals | 8 |
| Technology | Trench (OptiMOS 5) |
| RoHS Status | Compliant |
IPT026N10N5ATMA1 Pin Configuration
| Pin 1 | Source — Source connection (internally tied to thermal pad) |
| Pin 2 | Source — Source connection |
| Pin 3 | Source — Source connection |
| Pin 4 | Gate — Gate drive input |
| Pin 5 | Source — Source connection |
| Pin 6 | Source — Source connection |
| Pin 7 | Source — Source connection |
| Pin 8 | Drain — Drain connection (top side, exposed pad) |
Safe Operating Area (TC=25°C)
Typical Applications
IPT026N10N5ATMA1 is suitable for 6 applications: 48V Server and Telecom Synchronous Rectification, Brushless DC Motor Drives, Hot-Swap and OR-ing Switches, Solar Micro-Inverter Power Stage, Class-D Audio Output Stage, E-Bike and Light Electric Vehicle Battery Switch.
48V Server and Telecom Synchronous Rectification
The IPT026N10N5ATMA1 fits 48 V server and telecom synchronous rectification because its 100 V VDS rating provides avalanche headroom on 48-60 V bus rails while the 2.6 mΩ RDS(on) keeps conduction loss under 5 W at 50 A output current. Placed as the low-side MOSFET in a half-bridge LLC or hard-switched buck stage, it replaces older D2PAK parts at 60 % smaller footprint. Compared to a 60 V MOSFET the 100 V rating eliminates avalanche stress during output-side transients. The 214 W power dissipation rating supports continuous 100 A operation at Tc=80 °C without external heatsinking beyond PCB copper.
Recommended
Brushless DC Motor Drives
In 48-72 V BLDC motor drives for industrial fans, pumps, and e-mobility auxiliaries, the IPT026N10N5ATMA1's 202 A continuous current and 2.6 mΩ RDS(on) reduce I²R losses by 30-50 % versus older 100 V parts. The trench OptiMOS 5 technology gives low Qgd (~25 nC typical) which enables 50-100 kHz PWM frequencies for quieter motor operation and reduced current ripple. Used in the three-phase inverter leg with a gate driver like the IR2110SPBF or 2EDL8034G4CXTMA1, the part handles regenerative-braking avalanche energy within its SOA. The TOLL footprint simplifies compact motor-controller PCB layouts.
Recommended
Hot-Swap and OR-ing Switches
The IPT026N10N5ATMA1 is well suited to telecom-board hot-swap and OR-ing switches on 48 V distribution rails because its 100 V VDS tolerates plug-in transient spikes up to 80 V while the 2.6 mΩ RDS(on) minimizes steady-state voltage drop. In OR-ing topologies the MOSFET replaces a Schottky diode, cutting power loss by 40-60 % and eliminating the heatsink. The part's SOA supports the brief inrush current when a board card is inserted into a live backplane. Built-in source-connected tab enables direct PCB cooling without external thermal management.
Recommended
Solar Micro-Inverter Power Stage
In solar micro-inverters operating from 40-60 V PV strings, the IPT026N10N5ATMA1 acts as the primary switching element at 100 kHz+ frequencies with its 2.6 mΩ RDS(on) and low Qg achieving >98 % conversion efficiency. The 100 V rating covers the maximum power-point voltage of typical residential PV strings with ample derating margin. Compared to planar MOSFETs of similar rating, OptiMOS 5's lower figure-of-merit cuts switching losses by 25-35 % at high frequency, allowing smaller magnetics. The TOLL package footprint reduces inverter box volume by 30-40 % versus conventional TO-247 designs.
Recommended
Class-D Audio Output Stage
The IPT026N10N5ATMA1 fits Class-D audio output stages up to 500 W per channel because its 2.6 mΩ RDS(on) reduces output-filter losses and its trench technology yields low distortion under high di/dt switching. The 100 V rating supports ±50 V supply rails typical of pro-audio amplifiers, while 202 A peak current handles low-impedance 4-ohm loads. The TOLL package enables compact amplifier modules by replacing larger TO-264 or D2PAK parts at one-quarter the PCB area. Source-connected tab provides thermal spreading without dedicated heatsinking at moderate continuous output.
Recommended
E-Bike and Light Electric Vehicle Battery Switch
In 48 V e-bike and light-EV battery management, the IPT026N10N5ATMA1 serves as the main discharge and pre-charge MOSFET handling up to 200 A peak with 2.6 mΩ RDS(on). The 100 V rating tolerates regen-braking spikes on the bus, while the TOLL package enables compact battery-pack BMS layouts. Compared to a TO-220 part, the surface-mount TOLL cuts assembly cost and improves vibration tolerance. Source-connected thermal tab couples directly to the BMS PCB copper, removing the heatsink from the BOM in most designs.
Recommended
Recommended Products Summary
Engineering reference data for IPT026N10N5ATMA1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | IPT015N10N5ATMA1 | IPT023N10N5ATMA1 | IPT027N10N5ATMA1 | BSC076N04NDATMA1 | IPC100N04S5L1R5ATMA1 |
|---|---|---|---|---|---|---|
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies |
| Package | PG-HSOF-8-1 (TOLL) | PG-HSOF-8-1 (TOLL) | PG-HSOF-8-1 (TOLL) | PG-HSOF-8-1 (TOLL) | PG-HSOF-8-1 (TOLL) | PG-HSOF-8-1 (TOLL) |
| VDS Max | 100 V | 100 V | 100 V | 100 V | 40 V | 40 V |
| RDS(on) Max @10V | 2.6 mΩ | 1.5 mΩ | 2.3 mΩ | 2.7 mΩ | 0.76 mΩ | 1.5 mΩ |
| Technology | OptiMOS 5 (Trench) | OptiMOS 5 (Trench) | OptiMOS 5 (Trench) | OptiMOS 5 (Trench) | OptiMOS 5 (Trench) | OptiMOS 5 (Trench) |
| VGS Max | ±20 V | ±20 V | ±20 V | ±20 V | ±20 V | ±20 V |
Key Differentiators
- Lower RDS(on) at same voltage than legacy 100V MOSFETs (vs Generic 100V D2PAK MOSFETs (~5 mΩ))
- 60% smaller PCB footprint than D2PAK (vs D2PAK (TO-263) MOSFETs)
- OptiMOS 5 platform with optimized FOM (vs Older OptiMOS 3 / OptiMOS 4 generations)
Design Notes
At continuous 100 A load with RDS(on)=2.6 mΩ, conduction loss is approximately 26 W; this must be sunk through PCB copper to the TOLL source-connected thermal pad. Infineon's application note recommends a minimum 25x25 mm 2 oz copper pad on each source pin to keep junction temperature below 125 °C at TA=70 °C. Without adequate copper the junction will exceed thermal ratings within seconds at full load. Forced-air cooling or an attached heatsink may be required for continuous 150 A+ operation in enclosed boxes.
Place the gate-drive resistor (typically 10-33 Ω) within 5 mm of pin 4 to dampen parasitic gate-source ringing. Use a Kelvin-source connection if the layout allows: a separate trace from source-sensing to the gate-driver ground eliminates the source-inductance voltage drop from the gate-drive loop. For high di/dt switching at 100 kHz+, keep the high-current drain-source loop area below 100 mm² to limit parasitic inductance and the resulting VDS overshoot during turn-off.
Do not operate the IPT026N10N5ATMA1 above VGS=±20 V - the gate oxide will rupture. Use a 12 V or 10 V gate-drive supply with adequate decoupling. Avoid plugging the part into a live circuit without soft-start; the body-diode reverse recovery can produce severe dV/dt ringing. For OR-ing and hot-swap applications, gate-them-off with a controlled ramp to limit inrush. Lastly, never exceed TJ=175 °C even briefly - the OptiMOS 5 silicon will thermally run away above this limit.
The TOLL package's eight source pins must all be soldered to maximize current-carrying capacity and thermal spreading; leaving pins unsoldered creates localized hotspots that degrade long-term reliability. Use a reflow profile compatible with MSL1 or MSL2 moisture sensitivity - the TOLL package is rated MSL2 per JEDEC J-STD-020. Avoid manual soldering on this package because the thermal pad makes hand-rework unreliable; use a hot plate or dedicated rework station.
Compliance Information
RoHS and REACH compliance per Infineon product page. Not AEC-Q100 qualified; for automotive use consider the automotive-grade OptiMOS 5 variants in same TOLL package.
