IQE013N04LM6ATMA1 - 40V 1.35mΩ OptiMOS N-FET, PQFN 3.3x3.3 | Infineon
MPN: IQE013N04LM6ATMA1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1.58 | $1.58 |
| 10 | $1.42 | $14.20 |
| 100 | $1.18 | $118.00 |
| 500 | $0.98 | $490.00 |
| 1,000 | $0.84 | $840.00 |
| 3,000 | $0.71 | $2,130.00 |
Drop-in alternatives for IQE013N04LM6ATMA1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
IQE020N04LM6CGATMA1
✅ Drop-In✓ In Stock
$1.75 / Unit
View Datasheet →IQE008N03LM5SCATMA1
✅ Drop-In✓ In Stock
$1.18 / Unit
View Datasheet →IQE065N10NM5CGSCATMA1
✅ Drop-In✓ In Stock
$1.28 / Unit
View Datasheet →ISK057N04LM6ATSA1
✅ Drop-In✓ In Stock
$0.3 / Unit
View Datasheet →VBQF1402
✅ Drop-In📋 Reference alternative (not in catalog)
IQE013N04LM6ATMA1 Maximum Ratings & Electrical Characteristics
| Technology | OptiMOS N-channel trench MOSFET |
| Polarity | N-Channel |
| Drain-Source Voltage (VDS) | 40 V |
| Gate-Source Voltage (VGS) | ±20 V |
| Continuous Drain Current (Ta) | 31 A |
| Continuous Drain Current (Tc) | 205 A |
| Power Dissipation (Ta) | 2.5 W |
| Power Dissipation (Tc) | 107 W |
| On-Resistance RDS(on) typ | 1.35 mΩ @ VGS=10 V, ID=20 A |
| Gate Threshold Voltage (VGS(th)) | 2 V (typ) |
| Package | PG-TSON-8-4 / PQFN 3.3x3.3 mm Source-Down |
| Operating Temperature Range | -55 °C to +175 °C |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Source-Down Topology | Yes (flip-chip die attach, drain on top thermal pad) |
IQE013N04LM6ATMA1 Pin Configuration
| Pin 1 | Source — Source pad (Source-Down topology, top-side PCB) |
| Pin 2 | Source — Source pad |
| Pin 3 | Source — Source pad |
| Pin 4 | Source — Source pad |
| Pin 5 | Gate — Gate pad (drive input) |
| Pin 6 | Source — Source pad |
| Pin 7 | Source — Source pad |
| Pin 8 | Source — Source pad |
| Pin EP | Drain — Drain thermal pad (exposed, bottom side) |
Safe Operating Area
Typical Applications
IQE013N04LM6ATMA1 is suitable for 6 applications: 24V Telecom Point-of-Load Converter, Synchronous Rectification in SMPS, USB-PD and Battery Protection, Motor Drive Half-Bridge, Hot-Swap and OR-ing Controller, E-Mobility Battery Management.
24V Telecom Point-of-Load Converter
The IQE013N04LM6ATMA1 fits 24V telecom POL converters where the 40V VDS rating provides comfortable headroom over a 24V bus with switching transients, while 1.35 mΩ RDS(on) minimizes conduction loss at the 10-30 A loads typical of brick and POL stages. Placed as the synchronous rectifier on the low-side of a buck topology, the Source-Down PQFN routes high current through PCB top copper for efficient cooling, supporting junction temperatures below 100 °C with proper copper area. Compared with a D²PAK MOSFET, the 3.3x3.3 mm footprint roughly halves board area while delivering comparable thermal performance thanks to the Source-Down topology. Use a VGS=10 V gate drive to achieve the 1.35 mΩ RDS(on) typ and avoid continuous operation above ~15 A without verifying junction temperature rise.
Recommended
Synchronous Rectification in SMPS
In isolated SMPS such as 48 V-to-12 V or 24 V-to-5 V converters, the IQE013N04LM6ATMA1 serves as a synchronous rectifier MOSFET on the secondary side, replacing Schottky diodes to cut rectification loss by 60-80 percent. Its 1.35 mΩ RDS(on) at VGS=10 V and 31 A continuous TA rating support output currents up to ~20 A with appropriate copper area on the Source-Down pads. The Source-Down package topology eliminates bond-wire source inductance, enabling cleaner switching edges and reduced ringing on the secondary-side waveform. Compared with DPAK alternatives the Source-Down PQFN doubles power density. Pay attention to dead-time control to prevent shoot-through and monitor body-diode reverse recovery behaviour under CCM operation.
Recommended
USB-PD and Battery Protection
The IQE013N04LM6ATMA1 is well suited to USB-PD source and sink switches and to 12V/24V battery protection FETs where 40 V VDS provides ample margin over the bus voltage while the 1.35 mΩ RDS(on) keeps conduction loss below 0.5 W at 20 A continuous. The Source-Down PQFN package supports eFuse topologies that integrate the MOSFET and sense resistor on the same PCB top layer for fast short-circuit response. Compared with conventional DFN MOSFETs the Source-Down topology reduces thermal loop inductance, enabling faster trip times in hot-swap events. Verify SOA curves and EAS rating against inrush conditions before using in unclamped hot-swap designs, and add TVS protection across drain-source for inductive load transients.
Recommended
Motor Drive Half-Bridge
The IQE013N04LM6ATMA1 functions as a low-side or high-side switch in 24V/36V BLDC and brushed-motor half-bridges where its 205 A pulsed drain current supports the inrush and stall-current transients of small industrial motors. The Source-Down PQFN package allows compact H-bridge layouts on FR4 with sufficient top-layer copper for thermal management. Compared with through-hole TO-220 alternatives the surface-mount Source-Down footprint reduces assembly cost and enables bottom-side cooling via thermal vias. The 1.35 mΩ RDS(on) at full gate drive keeps I²R losses under 5 W at 60 A pulsed, well within the 107 W package dissipation limit at TC=25 °C.
Recommended
Hot-Swap and OR-ing Controller
For 12V/24V hot-swap and OR-ing applications the IQE013N04LM6ATMA1 acts as the main pass-FET, leveraging 1.35 mΩ RDS(on) for low insertion loss while the 40 V VDS rating provides safety margin during load-dump transients on 24V industrial buses. The Source-Down topology simplifies PCB layout by exposing the drain through the thermal pad for direct heatsinking, keeping junction temperature below 150 °C during continuous 30 A operation. Compared with DPAK OR-ing FETs the Source-Down PQFN roughly halves footprint area. Add a dedicated hot-swap controller such as BTS70081EPAXUMA1 or a discrete charge-pump gate driver for inrush control, and place a TVS across drain-source for transient protection.
Recommended
E-Mobility Battery Management
In low-voltage e-mobility battery management (e-bike, e-scooter, light EV auxiliary rails at 12 V-24 V), the IQE013N04LM6ATMA1 serves as a battery disconnect or pre-charge MOSFET, taking advantage of the 40 V VDS rating for transient safety and the 1.35 mΩ RDS(on) to minimize quiescent power loss. The Source-Down PQFN supports compact BMS layouts that integrate FETs, shunt resistor, and protection ICs on the same PCB top layer. Compared with larger TO-220 or D²PAK FETs, the 3.3x3.3 mm package enables tighter cell-module packaging. The 175 °C maximum junction temperature supports under-hood thermal environments when paired with adequate PCB copper flood and thermal vias.
Recommended
Recommended Products Summary
Engineering reference data for IQE013N04LM6ATMA1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | IQE020N04LM6CGATMA1 | IQE008N03LM5SCATMA1 | IQE065N10NM5CGSCATMA1 | ISK057N04LM6ATSA1 | VBQF1402 |
|---|---|---|---|---|---|---|
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | VBsemi |
| Package | PQFN 3.3x3.3 Source-Down (PG-TSON-8-4) | PQFN 3.3x3.3 Source-Down - same | PQFN 3.3x3.3 Source-Down - same family | PQFN 3.3x3.3 Source-Down - same family | PQFN 3.3x3.3 Source-Down - same family | PQFN 3.3x3.3 Source-Down footprint |
| Drain-Source Voltage VDS | 40 V | 40 V | 30 V | 100 V | 40 V | 40 V |
| RDS(on) typ @ VGS=10V | 1.35 mΩ | 2.0 mΩ | 0.8 mΩ | 6.5 mΩ | 5.7 mΩ | [DATA_NEEDED] |
| Continuous Drain Current (Tc) | 205 A | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Power Dissipation (Tc) | 107 W | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Gate Threshold Voltage | 2 V (typ) | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Source-Down Topology | Yes | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- Industry-lowest RDS(on) per footprint in 40V OptiMOS Source-Down family (vs IQE020N04LM6CGATMA1)
- Source-Down topology doubles usable copper area vs conventional DFN (vs Standard DFN MOSFETs)
- Higher VDS rating than 30V Source-Down alternatives for safety margin (vs IQE008N03LM5SCATMA1)
Design Notes
Estimated: at ID=30 A continuous and RDS(on)=1.35 mΩ, conduction loss is ~1.2 W. With junction-to-ambient thermal resistance of ~50 °C/W on a 1 square inch copper flood, junction temperature rise is roughly 60 °C above ambient, which is acceptable below 90 °C ambient. The Source-Down topology requires top-layer copper flood plus a thermal-via array under the drain thermal pad. Skipping the via array and operating at high continuous current will overheat the device regardless of copper area, because the Source-Down design relies on via conduction to internal copper planes for heat spreading. Always compute RθJA from your actual PCB stack-up, not from the generic datasheet value, since PCB design dominates thermal performance in this package.
Use the exact Source-Down land pattern from the Infineon package outline, not a generic PQFN-8 footprint. The Source-Down pad geometry is not symmetric: gate pad sits at one corner, source pads surround the drain thermal pad, and the dimensions differ slightly from conventional DFN packages. Place the gate drive traces on an inner layer to avoid capacitive coupling to the source pads, which can cause unwanted turn-on. Keep the high-current source return on the top copper layer with minimum 1 oz copper and a flood area at least equal to the package footprint.
Source-Down topology minimizes source inductance by eliminating bond wires, but the gate loop still requires careful routing. Keep gate drive traces short (<5 mm), surround them with a ground-source flood on the same layer, and place a small gate-source resistor (10-100 Ω) close to the gate pad to dampen ringing. Avoid routing gate traces parallel to drain traces on adjacent layers to prevent dv/dt-induced false turn-on. For high-frequency switching above 200 kHz, consider using a dedicated gate-driver IC such as 2EDL8124GXUMA1 with integrated dead-time control.
Common pitfalls: (1) Using a generic PQFN-8 land pattern instead of the Source-Down-specific pattern leads to poor solder joint reliability. (2) Operating at VGS below 8 V raises RDS(on) dramatically and may push the device into linear-region operation. (3) Avalanche energy (EAS) ratings must be checked for unclamped inductive switching; the Source-Down package has limited EAS compared with through-hole TO-220. (4) Maximum VGS of ±20 V is absolute; transients above this will rupture the gate oxide. Add a gate-source Zener clamp of 16-18 V for protection in noisy environments.
Compliance Information
RoHS and lead-free status inferred from manufacturer product page and distributor listings; AEC-Q100 not stated in verified data so flagged not_applicable. Halogen-free status not stated in verified data.
