LFE2-35E-7F672C - 32K LUT ECP2 FPGA, 450 I/O, 672-BBGA | Lattice
MPN: LFE2-35E-7F672C ✓ ActiveLFE2-35E-7F672C Overview
An FPGA is a programmable semiconductor whose logic fabric, memory and interconnect are configured at power-up from a non-volatile configuration memory. Where an ASIC fixes a function in silicon, an FPGA lets a designer reconfigure the same package pinout for different logic, interface or DSP tasks, shortening development cycles and supporting field upgrades. The ECP2 family sits at the low-cost, high-volume end of Lattice's portfolio and is widely used for control, interface and signal-processing logic that does not require the resources of a midrange FPGA.
Key features of this device include 32,000 LUTs (reported as 32K LUTs by distributor listings), a 339,968 gate count, and 450 general-purpose I/O in a single square BGA package with ball terminals. The 1.2 V core supply keeps on-board power dissipation manageable in dense control designs, and the -7 speed grade is the fastest ordering option in the ECP2 line, which matters for timing closure on multi-cycle bus and pipeline-heavy logic. The family also supports dedicated DSP and memory resources for arithmetic and buffer-heavy data paths.
Technologically the part belongs to the ECP2 low-cost architecture, where the logic fabric is built from 4-input LUTs with dedicated block RAM and DSP multipliers. Because configuration is non-volatile, the device boots directly into the loaded bitstream without an external configuration PROM, which reduces board area and BOM cost on production builds. Exact block counts for DSP multipliers and block RAM for this ordering code are listed as and in the specification table; consult the manufacturer datasheet for the definitive resource breakdown before finalizing a design.
Typical applications for this device include industrial control and factory automation modules, video timing and interface bridging, audio and general DSP pipelines, network and data-communication interface cards, and instrumentation front ends. The high I/O count of 450 in a single 672-ball package makes it especially useful where many parallel lines, memory interfaces and differential pairs must converge on one device.
When designing around this FPGA, budget for the BGA escape-routing density of a 672-ball package, match the printed board stack-up to the manufacturer's ball-pitch and land-pattern recommendations, and confirm the -7 speed grade timing margin against your slowest clock domain. Use the Request a Quote form on this page for current pricing, stock and lead time on this exact ordering code.
This page consolidates manufacturer-family specifications, distributor availability and drop-in alternatives for the LFE2-35E-7F672C, plus practical design notes, a parameter-by-parameter comparison table and application guidance that go beyond a bare catalog listing.
Drop-in alternatives for LFE2-35E-7F672C — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LFE2-35E-7F672C (same form factor and footprint) — differing in Device Type, Package, Maximum Frequency, Package Type, Speed Grade.
LFE2-35E-6F672C
✅ Drop-InContact for price
View Datasheet →LFE2-35SE-7F672C
✅ Drop-In📋 Reference alternative (not in catalog)
LFE2-35E-5F672C
✅ Drop-In ⚠️ Specs UnverifiedContact for price
View Datasheet →LFE2-25E-7F672C
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LFE2-20E-7F672C
✅ Drop-In ⚠️ Specs UnverifiedContact for price
View Datasheet →LFE2-20SE-7F672C
✅ Drop-In📋 Reference alternative (not in catalog)
LFE2-35E-7F672C Maximum Ratings & Electrical Characteristics
| Device Type | ECP2 Field Programmable Gate Array (FPGA) |
| Number of LUTs | 32,000 (32K LUTs) |
| Gate Count | 339,968 gates |
| Number of I/O | 450 I/O |
| Core Supply Voltage | 1.2 V |
| Speed Grade | -7 |
| Package | 672-BBGA (square BGA, ball terminals) |
| Number of Terminals | 672 |
| Form of Terminal | Ball |
| Package Shape | Square |
| Mounting Type | Surface Mount |
| DSP Support | Yes (ECP2 family DSP resources) |
| Operating Temperature Grade | Other |
| Supplier Packaging Code | 672-FP BGA (FPBGA) |
LFE2-35E-7F672C square Pin Configuration Guide
Pin configuration for LFE2-35E-7F672C (square package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for LFE2-35E-7F672C.
Refer to the datasheet for full pin configuration.
Typical Applications
LFE2-35E-7F672C is suitable for 6 applications: Industrial Control and Automation, Video Timing and Display Interface Bridging, Audio and General DSP Pipelines, Communications and Network Interface Cards, Instrumentation and Test & Measurement Front Ends, Edge Gateways and IoT Control Nodes.
Industrial Control and Automation
The LFE2-35E-7F672C suits machine-control and factory automation modules because it combines 32,000 LUTs with 450 user I/O in one 672-ball device. That I/O headroom lets one FPGA absorb discrete field-bus I/O, encoder and limit-switch inputs, solenoid and stepper outputs, plus a safety-monitoring path, instead of splitting the design across a PLD and an MCU. The -7 speed grade gives margin on position-control loops that would otherwise close timing at a lower bin, and the 1.2 V core keeps the logic rail efficient in a cabinet with limited thermal budget. Use the I/O pin table from the manufacturer datasheet to plan the 3.3 V and 5 V tolerant banks against your sensor and drive levels.
Recommended
Video Timing and Display Interface Bridging
In video capture, display-driver and scaler modules the LFE2-35E-7F672C can absorb wide parallel data paths and timing generators. The 450 user I/O count covers multi-channel pixel buses, sync and blanking signals, and control lines to an external display or image-sensor interface without forcing external glue logic, while 32,000 LUTs hold timing counters, color-space converters and alpha-blending pipelines. Because the ECP2 architecture includes dedicated DSP resources, chroma and scaling arithmetic can be mapped to hardware multipliers rather than consuming general logic, and the -7 grade shortens the pipeline latency between input capture and output display. Keep pixel-clock jitter margins in mind and route the parallel bus as length-matched pairs on a solid reference plane.
Recommended
Audio and General DSP Pipelines
The LFE2-35E-7F672C targets audio codecs, filter banks, mixer and effect pipelines where arithmetic density matters as much as control logic. 32,000 LUTs and the ECP2 DSP multiplier resources allow FIR and biquad stages to be pipelined at high clock rates while leaving fabric capacity for a control and interface block handling S/PDIF or I2S framing, channel routing and status reporting. The -7 speed grade supports deeper pipelining per stage, which improves timing closure at 48-192 kHz sample rates with heavy oversampling. Use dedicated DSP blocks for multiply-accumulate loops and reserve LUT logic for control, and keep the audio reference clock on a dedicated low-jitter route away from switching outputs.
Recommended
Communications and Network Interface Cards
For protocol bridging, aggregation and line-card interface designs, the LFE2-35E-7F672C provides the parallelism needed to terminate many lanes while running a state machine, FIFO and packet-processing core in the fabric. The 450 user I/O in a 672-ball package suits designs that need several parallel byte-wide buses, multiple transceiver interfaces and a management interface without an external bus switch. With 1.2 V core operation and the fastest -7 grade of the ECP2 family, timing margin is available for wide internal buses and deeply pipelined datapaths. Pair the FPGA with an Ethernet PHY or SerDes and isolate high-speed clocks carefully to preserve the low jitter required for reference clocks and recovery loops.
Recommended
Instrumentation and Test & Measurement Front Ends
The LFE2-35E-7F672C is a natural fit for instrument front ends that must sequence measurements, run calibration routines and format results for a host interface. Its 32,000 LUTs provide room for multi-channel acquisition control, trigger logic, averaging and filter chains, and the 450 I/O allow direct attachment of sensor inputs, relay drivers and display/serial ports on a single board. The -7 grade keeps acquisition and processing loops deterministic enough for timing-sensitive measurement windows, and non-volatile configuration means the instrument powers up ready to run without an external configuration PROM. Design the analog and digital domains apart by keeping the FPGA's switching edges away from the reference and measurement ground returns.
Recommended
Edge Gateways and IoT Control Nodes
Edge nodes that aggregate sensors, run protocol translation and buffer local storage benefit from the LFE2-35E-7F672C's combination of logic depth and pin count in a single package. It can host a small CPU-equivalent soft core, a bus master for external flash or SDRAM, and the logic needed to bridge two or three field protocols simultaneously, while the 450 I/O remove the need for I/O expanders. The 1.2 V core supply lowers system power in always-on deployments compared with higher-voltage logic, and the -7 grade gives comfortable timing margin for packet handling at 100 MHz-plus internal rates. Choose a package with exposed thermal relief for the logic core region if the design runs sustained traffic at high switching activity.
Recommended
Recommended Products Summary
Engineering reference data for LFE2-35E-7F672C — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LFE2-35E-6F672C | LFE2-35SE-7F672C | LFE2-35E-5F672C | LFE2-25E-7F672C | LFE2-20E-7F672C |
|---|---|---|---|---|---|---|
| Package | 672-BBGA | 672-BBGA - same | 672-BBGA - same | 672-BBGA - same | 672-BBGA - same | 672-BBGA - same |
| Brand | Lattice Semiconductor | Lattice Semiconductor | Lattice Semiconductor | Lattice Semiconductor | Lattice Semiconductor | Lattice Semiconductor |
| Core Supply Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
| Speed Grade | -7 | -6 | -7 (SE bin) | -5 | -7 | -7 |
| Device Type | ECP2 FPGA | ECP2 FPGA | ECP2 FPGA | ECP2 FPGA | ECP2 FPGA | ECP2 FPGA |
| Terminals / Package Form | 672 ball terminals, square BGA | 672 ball terminals, square BGA | 672 ball terminals, square BGA | 672 ball terminals, square BGA | 672 ball terminals, square BGA | 672 ball terminals, square BGA |
Key Differentiators
- Highest speed grade in the ECP2 line at the same logic density and pin count (vs LFE2-35E-6F672C)
- Substantially higher logic and I/O density than smaller ECP2 codes in the identical package (vs LFE2-25E-7F672C)
- Single-package consolidation of control, DSP and high-pin-count interface logic (vs LFE2-20E-7F672C)
Design Notes
A 672-ball fine-pitch BGA is the dominant assembly constraint for this device, not the logic itself. Plan the stack-up so that every ball can escape on the same layer count used by your assembly house, reserve via-in-pad or filled microvias under the device, and keep the fanout region free of plane splits that would force layer changes for inner balls. Confirm the ball-pitch and land-pattern dimensions against the Lattice ECP2 package drawing rather than copying a generic BGA footprint; a mechanical mismatch here is unrecoverable after fabrication.
Separate the 1.2 V core rail from the I/O rails with its own filtering, and estimate dissipation from switching activity rather than from nominal device power alone: Estimated, assuming roughly 30% average logic utilisation with 32,000 LUTs at 1.2 V core and about 6 mW per active LUT at mid-frequency activity, the core alone is on the order of 0.06-0.10 W, while I/O banks add dynamic current proportional to edge rate on the 450 user I/O. Provide copper area under the device for heat spreading, verify the power tree sequencing against the manufacturer guidance, and keep the 1.2 V rail noise low because it directly perturbs timing margin on the -7 grade.
Route clocks and high-speed buses first, with length matching applied to parallel pixel, byte-wide or DDR-style interfaces rather than as a post-layout correction. Because the device exposes 450 user I/O, plan a deliberate pin budget per bank and keep a reserve of spare I/O for bring-up debug; routed-out pins are the difference between a two-hour and a two-day debug cycle. Keep the configuration, clock and dedicated RAM/DSP pins from the manufacturer pin table on known-good layers, and avoid long stubs on any signal that enters the fabric as a high-frequency clock.
The most common mistake is assuming that any ECP2 in the same 672-ball package is interchangeable. Speed-grade changes (-7 to -6 or -5) are pin-compatible but change timing, so re-run static timing analysis after any substitution. A second common error is underestimating resource usage by implementing multipliers in LUT logic instead of the dedicated DSP blocks, which can exhaust the 32K LUT budget in an audio or filter design; map multiply-accumulate to DSP primitives first and keep LUT logic for control and interface functions.
Compliance Information
Material-compliance declarations for the ECP2 family are issued by Lattice per ordering code and date code; request the applicable declaration together with the quotation for this exact ordering code.
