STM32MP153AAC3 - Dual Cortex-A7 650MHz MPU | STMicroelectronics
MPN: STM32MP153AAC3 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $11.53 | $11.53 |
| 10 | $9.08 | $90.80 |
| 25 | $8.47 | $211.75 |
| 189 | $7.56 | $1,428.84 |
| 1,000 | $7 | $7,000.00 |
STM32MP153AAC3 Overview
A microprocessor unit (MPU) sits above a microcontroller (MCU) in the embedded-system hierarchy: unlike an MCU, an MPU relies on external DDR memory and boot media, enabling full operating systems such as Linux or Android. The STM32MP1 line bridges these worlds by pairing Cortex-A7 application cores with a Cortex-M4 MCU core, allowing a single chip to run Linux while servicing hard real-time tasks.
Key features include heterogeneous dual-core architecture (2x Cortex-A7 plus Cortex-M4), a TFT display controller for graphics interfaces, 37 communication interfaces, 29 timers, and advanced analog peripherals. The device operates from a 1.18V to 1.25V core supply and integrates the STM32 peripheral ecosystem familiar to STM32 MCU developers.
Architecturally, the Cortex-A7 subsystem handles the open-source OS stack, while the Cortex-M4 executes deterministic control loops with low latency and independent peripherals. OpenSTLinux distribution support and ST's STM32Cube ecosystem provide a complete software development environment spanning both cores.
Typical applications include industrial HMI panels, building automation gateways, programmable logic controllers, and connected devices requiring a display plus edge connectivity.
Design consideration: because the STM32MP153AAC3 has no internal DDR memory, PCB layout must respect DDR3/LPDDR2 length-matching rules and ST's documented power-sequencing requirements.
This page synthesizes distributor pricing, same-package family alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for STM32MP153AAC3 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
STM32MP153AAB3
β Drop-Inπ Reference alternative (not in catalog)
STM32MP151AAC3
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$6.3 / Unit
View Datasheet βSTM32MP151AAB3
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
STM32MP153DAC3
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
STM32MP157AAC3
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$5 / Unit
View Datasheet βSTM32MP153AAC3 Maximum Ratings & Electrical Characteristics
| Core | Dual Arm Cortex-A7 + Arm Cortex-M4 |
| Core Architecture | 32-bit, heterogeneous multicore (2 + 1 cores) |
| Maximum Clock Rate | 209 MHz to 650 MHz |
| Series | STM32MP1 |
| Display Controller | TFT |
| Communication Interfaces | 37 interfaces |
| Timers | 29 timers |
| Analog Peripherals | Advanced analog |
| Core Supply Voltage | 1.18 V to 1.25 V |
| Package | 361-TFBGA (12x12 mm) |
| Mounting Type | Surface Mount |
| Memory Type | External DDR (DRAM controller) |
| Real-Time Coprocessor | Arm Cortex-M4 |
| Product Family | STM32MP153A/D, Arm dual Cortex-A7 800 MHz + Cortex-M4 MPU |
| Packaging | Tray |
STM32MP153AAC3 361-tfbga (12x12 mm) Pin Configuration Guide
Pin configuration for STM32MP153AAC3 (361-tfbga (12x12 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for STM32MP153AAC3.
Refer to the datasheet for full pin configuration.
Typical Applications
STM32MP153AAC3 is suitable for 6 applications: Industrial HMI and TFT Display Panels, Building Automation and IoT Gateways, Programmable Logic Controllers (PLC), Connected Consumer and Smart Home Devices, Medical Device Control and Monitoring, Edge AI and Data Aggregation Nodes.
Industrial HMI and TFT Display Panels
The STM32MP153AAC3 is well suited to industrial human-machine interfaces because its integrated TFT display controller drives panels directly while the dual Cortex-A7 cores at up to 650 MHz run a Linux GUI stack such as Qt or Wayland under OpenSTLinux. The heterogeneous architecture lets the Cortex-M4 handle touch sampling, backlight PWM, and safety watchdogs deterministically while Linux renders graphics, avoiding UI stalls. With 37 communication interfaces, the same chip connects CAN, Ethernet, and RS-485 field buses. The 361-TFBGA (12x12 mm) footprint fits compact panel PCs, and the 1.18V-1.25V core rail is typically supplied by an STPMIC1 PMIC for sequenced power-up.
Recommended
Building Automation and IoT Gateways
For building automation and IoT edge gateways, the STM32MP153AAC3 provides the connectivity and protocol processing a gateway needs: the dual Cortex-A7 running Linux handles MQTT/TLS stacks, cloud connectors, and local web servers, while 37 communication interfaces cover Ethernet, multiple UARTs, SPI, I2C, and CAN for sensor and actuator networks. The Cortex-M4 coprocessor keeps protocol polling and fast I/O running even during Linux reboots or updates, improving system availability. The 650 MHz-class performance sustains encrypted traffic without an external accelerator in light-to-moderate workloads, and external DDR support scales memory to gateway buffering requirements.
Recommended
Programmable Logic Controllers (PLC)
In compact PLC designs, the STM32MP153AAC3 merges an IEC-class Linux runtime with hard real-time I/O on one chip. The dual Cortex-A7 executes the soft-logic engine, HMI, and fieldbus masters ( EtherCAT/CANopen via its 37 interfaces), while the Cortex-M4 core services high-speed counter inputs, PWM outputs, and trip protection with microsecond determinism. The 29 timers and advanced analog peripherals support accurate input filtering and pulse measurement. Using a single MP153 instead of a separate MPU plus MCU reduces BOM count and board area in the 361-TFBGA (12x12 mm) footprint, simplifying certification documentation.
Recommended
Connected Consumer and Smart Home Devices
Consumer products with a display and network connectivity - smart thermostats with panels, connected appliances, and wall controllers - benefit from the STM32MP153AAC3's balance of application processing and control integration. The TFT display controller plus Linux graphics provides a modern user interface at 650 MHz-class dual-core performance, while the Cortex-M4 runs always-on tasks such as button sensing and wireless module management, allowing the A7 domain to sleep for power savings. External boot from eMMC or SD keeps the bill of materials flexible across price points, and ST's long-term STM32MP1 supply commitment suits consumer product lifecycles.
Recommended
Medical Device Control and Monitoring
Portable and benchtop medical devices - patient monitors, infusion interfaces, and diagnostic instruments - use the STM32MP153AAC3 to combine a graphical UI with precise sensing. The advanced analog peripherals and 29 timers support accurate signal acquisition timing, while the Cortex-M4 executes deterministic acquisition loops isolated from Linux, easing software architecture for regulated development. The dual A7 cores at up to 650 MHz run data logging, networking, and display under OpenSTLinux, and 37 communication interfaces integrate USB, Ethernet, and instrument buses. The 12x12 mm TFBGA supports compact handheld form factors with careful PCB design.
Recommended
Edge AI and Data Aggregation Nodes
For industrial edge nodes that pre-process sensor data before cloud upload, the STM32MP153AAC3 provides the compute headroom and I/O breadth required. The dual Cortex-A7 at up to 650 MHz executes ST's STM32Cube.AI-deployed models on the M4 side or lightweight inference in Linux, while 37 communication interfaces aggregate data from RS-485, CAN, SPI, and I2C sensor clusters. The Cortex-M4 performs real-time filtering and anomaly detection continuously, with results passed to Linux for buffering and TLS-secured transmission. External DDR scaling accommodates ring-buffer datasets, and the active-lifecycle STM32MP1 family ensures multi-year sourcing.
Recommended
Recommended Products Summary
Engineering reference data for STM32MP153AAC3 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | STM32MP153AAB3 | STM32MP151AAC3 | STM32MP157AAC3 | STM32MP153DAC3 |
|---|---|---|---|---|---|
| Package | 361-TFBGA (12x12 mm) | 361-TFBGA (12x12 mm) - same | 361-TFBGA (12x12 mm) - same | 361-TFBGA (12x12 mm) - same | 361-TFBGA (12x12 mm) - same |
| Brand | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics |
| Cores | 2x Cortex-A7 + Cortex-M4 | 2x Cortex-A7 + Cortex-M4 | Cortex-A7 + Cortex-M4 (MP151 line) | 2x Cortex-A7 + Cortex-M4 + GPU | 2x Cortex-A7 + Cortex-M4 |
| Communication Interfaces | 37 interfaces | 37 interfaces | similar STM32MP1 interface set | similar STM32MP1 interface set | similar STM32MP1 interface set |
| Core Supply Voltage | 1.18 V to 1.25 V | 1.18 V to 1.25 V | 1.18 V to 1.25 V | 1.18 V to 1.25 V | 1.18 V to 1.25 V |
| Memory | External DDR controller | External DDR controller | External DDR controller | External DDR controller | External DDR controller |
| Lifecycle Status | Active | Active | Active | Active | Active |
Key Differentiators
- Heterogeneous dual Cortex-A7 + Cortex-M4 in one chip (vs STM32MP151AAC3)
- Lower cost than GPU-equipped sibling (vs STM32MP157AAC3)
- Speed-grade flexibility via ordering code (vs STM32MP153AAB3)
Design Notes
The STM32MP153AAC3 requires strictly sequenced power rails with the core at 1.18V to 1.25V plus separate I/O and DDR supplies. ST's reference design uses the STPMIC1 PMIC, which provides all rails with correct sequencing and watchdog-driven reset. Powering rails out of order can prevent boot or stress I/O structures. Budget for the external DDR supply rails as well; total system power depends strongly on DDR type and CPU load. Estimate: verify each rail's accuracy against the datasheet power-supply table before layout sign-off.
Because the STM32MP153AAC3 relies on external DDR3/LPDDR2 memory, follow the datasheet and ST application-note DDR routing rules: matched trace lengths within group, controlled impedance, and reference-plane continuity. The 361-ball TFBGA (12x12 mm) typically requires at least 6 layers for clean DDR fanout and power integrity. Use ST's STM32MP15 evaluation board layout as a template, and respect the ball-map fanout recommendations to escape signals without splitting ground planes.
A frequent mistake is treating the STM32MP153AAC3 like an MCU: it boots from external media (eMMC/NAND/SD/QSPI) through ROM code with specific boot-pin strap configurations - get the BOOT0/BOOT1 strapping wrong and the board will not start. Also plan the Cortex-M4 memory partitioning and mailbox communication early; retrofitting A7/M4 resource sharing after layout is costly. Validate thermal dissipation under sustained Linux load with realistic heatsinking per the package thermal data.
Compliance Information
Compliance status not stated in the provided web data; verify on the official ST product page or datasheet before design-in.
