STM32MP151AAC3 - Cortex-A7 650MHz MPU TFBGA-361 | STMicroelectronics
MPN: STM32MP151AAC3 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $9.74 | $9.74 |
| 10 | $8.4 | $84.00 |
| 30 | $7.23 | $216.90 |
| 100 | $6.55 | $655.00 |
| 500 | $6.3 | $3,150.00 |
STM32MP151AAC3 Overview
A microprocessor unit (MPU) sits above the microcontroller (MCU) in the embedded-processing hierarchy: unlike an MCU, an MPU runs a full OS such as Linux and delegates hard real-time tasks to a companion Cortex-M core. The STM32MP1 series bridges both worlds on one die, allowing Linux on the Cortex-A7 and deterministic control on the Cortex-M4 with shared peripherals and inter-processor communication.
Key features include 35 communication interfaces (UART, SPI, I2C, CAN, USB, Ethernet MAC and more), 25 timers, and a TFT display controller for direct LCD interfacing. The device operates from a nominal core supply of 1.18 V to 1.25 V, with multi-rail power architecture typical of the STM32MP1 family. According to the ST product page, the STM32MP151A/D family is based on the high-performance Arm Cortex-A7 32-bit RISC core.
Architecturally, the Cortex-A7 delivers the performance of a cost-effective Linux-capable applications processor, while the Cortex-M4 at 209 MHz shares the same peripheral set, enabling a true heterogeneous design. The TFT controller supports external display panels, making the part a single-chip HMI engine. There is no hardware crypto or secure boot in the STM32MP151 base configuration.
Typical applications include industrial HMIs with TFT touch displays, building automation gateways, motor control systems combining Linux connectivity with real-time control, and IoT edge nodes. Per the alldatasheet description, the part integrates Arm Cortex-A7 650 MHz plus Cortex-M4 MPU, TFT, 35 communication interfaces and 25 timers.
When designing, budget the multi-rail power tree carefully - VDDCORE requires 1.18-1.25 V - and plan for external DDR memory and boot media, as the MPU has no on-chip run-in system RAM for Linux.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for STM32MP151AAC3 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with STM32MP151AAC3 (same form factor and footprint) β differing in Core Processor, Package, Architecture, Number of Cores, Security.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
STM32MP151CAC3T
β Drop-Inπ Reference alternative (not in catalog)
STM32MP153CAA3
β Drop-Inπ Reference alternative (not in catalog)
STM32MP153CAC3
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
Contact for price
View Datasheet βSTM32MP157CAA3
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
STM32MP157CAC3
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$24.2 / Unit
View Datasheet βSTM32MP151AAC3 Maximum Ratings & Electrical Characteristics
| Core Processor | Arm Cortex-A7 32-bit RISC |
| Core Clock (Max) | 650 MHz |
| Coprocessor | Arm Cortex-M4 at 209 MHz |
| Number of Cores | 2 (1x Cortex-A7 + 1x Cortex-M4) |
| Architecture | 32-bit |
| Series | STM32MP1 (STM32MP151A) |
| Core Supply Voltage | 1.18 V to 1.25 V |
| Communication Interfaces | 35 interfaces |
| Timers | 25 timers |
| Display Controller | TFT |
| Package / Case | TFBGA-361 (12x12 mm) |
| Mounting Type | Surface Mount |
| Hardware Crypto / Secure Boot | No (STM32MP151 base configuration) |
| Packaging | Tray |
| RoHS Status | Compliant |
STM32MP151AAC3 tfbga-361 (12x12 mm) Pin Configuration Guide
Pin configuration for STM32MP151AAC3 (tfbga-361 (12x12 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for STM32MP151AAC3.
Refer to the datasheet for full pin configuration.
Typical Applications
STM32MP151AAC3 is suitable for 6 applications: Industrial HMI with TFT Display, Industrial IoT Edge Gateway, Motor Control with Linux Supervision, Building Automation Controller, Test and Measurement Instrumentation, Smart Home and IoT Hub.
Industrial HMI with TFT Display
The STM32MP151AAC3 fits industrial human-machine interface terminals because its TFT display controller drives LCD panels directly while the 650 MHz Cortex-A7 runs a Linux UI stack such as Qt. The 209 MHz Cortex-M4 coprocessor handles capacitive touch scanning and real-time front-panel I/O independently of the OS, keeping the interface responsive even under Linux load. With 35 communication interfaces available for CAN, RS-485 and Ethernet-adjacent connectivity, one chip consolidates display, control and field communication. Designers should budget external DDR and eMMC/NAND boot media, as the MPU relies on external memory for the Linux stack.
Recommended
Industrial IoT Edge Gateway
As an edge gateway processor, the STM32MP151AAC3 provides Linux-capable Cortex-A7 performance at 650 MHz for protocol translation, MQTT/OPC UA stacks and local data buffering, while the Cortex-M4 at 209 MHz services deterministic sensor sampling and actuator timing. The 35 integrated communication interfaces minimize external bridge components when wiring UART, SPI, I2C and CAN field devices. Its 1.18-1.25 V core rail integrates into standard multi-rail PMIC power trees such as ST-recommended STM32MP1 companion power parts. For designs demanding wired Ethernet, the STM32MP153 sibling in the same package is the natural upgrade path without board respin.
Recommended
Motor Control with Linux Supervision
The heterogeneous architecture makes the STM32MP151AAC3 well suited to advanced motor drives: the Cortex-M4 core at 209 MHz executes hard real-time FOC current loops using the family timer resources (25 timers available), while the Cortex-A7 runs Linux for commissioning UIs, remote monitoring and cloud connectivity. The TFT controller enables local operator panels on drive units. Because both cores share the peripheral set and inter-processor communication is native to the STM32MP1 platform, no external real-time coprocessor is needed. Designers must verify timer assignments per the ST reference manual for their specific motor-control topology.
Recommended
Building Automation Controller
Building automation nodes benefit from the STM32MP151AAC3 combination of Linux connectivity (BACnet, Modbus TCP stacks run comfortably on the 650 MHz Cortex-A7) and real-time control on the Cortex-M4 for HVAC loops, lighting dimming and access-control timing. The 35 communication interfaces cover the RS-485, UART, I2C and SPI mix typical of field device integration, and the TFT controller supports wall-mounted panel displays. The 361-ball TFBGA 12x12 mm footprint keeps controller boards compact for DIN-rail or flush-mount enclosures, and the RoHS-compliant lead-free package suits commercial building products.
Recommended
Test and Measurement Instrumentation
Benchtop and portable instruments use the STM32MP151AAC3 as a Linux-based control engine: the Cortex-A7 manages the measurement sequencer, TFT touch UI and USB/Ethernet remote interfaces (SCPI over LAN), while the Cortex-M4 performs time-critical trigger handling and sample timing using the 25-timer resource pool. The 650 MHz core comfortably runs instrument firmware built on the STM32Cube MPU ecosystem and OpenSTLinux distribution. External DDR memory sizing is the main design decision - 512 MB to 1 GB is typical for instrument-class firmware images. The 12x12 mm package supports compact portable instrument PCBs.
Recommended
Smart Home and IoT Hub
Smart-home hubs leverage the STM32MP151AAC3 to run Linux middleware (Zigbee/Wireless stacks via attached radios, local automation rules, voice-assistant front ends) on the Cortex-A7, with the Cortex-M4 handling sensor polling and radio co-processor timing at 209 MHz. The 35 communication interfaces integrate multiple radio modules, sensors and peripherals over UART/SPI/I2C without external expanders, and the TFT controller supports countertop hub displays. Its RoHS-compliant TFBGA-361 package suits consumer-grade assembly. For hubs requiring hardware security and secure boot, evaluate security-enabled STM32MP1 variants in the same footprint.
Recommended
Recommended Products Summary
Engineering reference data for STM32MP151AAC3 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | STM32MP151CAC3T | STM32MP153CAA3 | STM32MP157CAA3 | STM32MP157CAC3 |
|---|---|---|---|---|---|
| Package | TFBGA-361 (12x12 mm) | TFBGA-361 (12x12 mm) - same | TFBGA-361 (12x12 mm) - same | TFBGA-361 (12x12 mm) - same | TFBGA-361 (12x12 mm) - same |
| Brand | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics |
| Cortex-A7 Core Speed | 650 MHz | 650 MHz class | 650 MHz class | 650 MHz class | 650 MHz class |
| Cortex-M4 Coprocessor | 209 MHz | 209 MHz | 209 MHz | 209 MHz | 209 MHz |
| CAN / Ethernet Peripheral Emphasis | Base peripheral set | Base peripheral set | Adds CAN-FD / Ethernet | Adds CAN-FD / Ethernet | Adds CAN-FD / Ethernet |
| Graphics Acceleration | TFT controller only | TFT controller only | TFT controller only | Adds GPU | Adds GPU |
| Core Supply Voltage | 1.18 V to 1.25 V | 1.18 V to 1.25 V | 1.18 V to 1.25 V | 1.18 V to 1.25 V | 1.18 V to 1.25 V |
Key Differentiators
- Lowest-cost STM32MP1 entry point in the TFBGA-361 footprint (vs STM32MP157CAC3)
- Heterogeneous dual-core architecture on a single die (vs STM32MP153CAA3)
- Drop-in upgrade path within the same 361-ball footprint (vs STM32MP151CAC3T)
Design Notes
The STM32MP151AAC3 uses a multi-rail power architecture with VDDCORE specified at 1.18 V to 1.25 V, plus separate I/O and DDR rails. ST recommends dedicated PMIC solutions for the STM32MP1 platform (e.g., the STPMIC1 family) which sequences VDDCORE, VDD_DDR and VDDQ in the required order. Estimate: core current depends on load frequency - at 650 MHz, budget for the worst-case core current listed in the datasheet power tables rather than typical values. Incorrect rail sequencing is one of the most common causes of MP1 boot failure, so validate power-up order on first prototypes.
The TFBGA-361 12x12 mm package requires controlled-impedance layout for DDR interface routing. Follow ST's hardware development application notes for the STM32MP1 platform: length-match DDR address/command groups, maintain the recommended DDR routing topology, and place the PMIC decoupling network close to the ball array. The 0.8 mm ball pitch is hand-routable on 6+ layer boards; 4-layer designs may struggle with DDR breakout. Use via-in-pad or dog-bone escape patterns per the ST reference design layout files.
The STM32MP151AAC3 has no on-chip memory suitable for running Linux - you must select and design in external boot media (eMMC, NAND or SD) and external DDR. Boot mode is configured via boot pins sampled at reset; mis-strapped boot pins produce silent non-boot conditions. Also note the STM32MP151 base configuration lacks hardware crypto and secure boot; if product security requirements emerge later, the same-footprint security-enabled STM32MP1 variants avoid a respin. Verify the exact ordering-code suffix against the ST ordering-information table before release.
Estimate: at 650 MHz with typical core current (use datasheet typical ICC values for your VDDCORE and frequency point), junction temperature rise over ambient is modest for the 12x12 mm TFBGA on a standard 4-layer PCB, but sustained 100% core load in enclosed industrial enclosures requires verification. ST provides thermal design guidance and theta-JA data in the datasheet thermal characteristics section; use those published values rather than generic BGA estimates when closing the thermal budget for sealed enclosures.
Compliance Information
RoHS and REACH compliance indicated by distributor attribute listings (JAK Electronics, Mouser). AEC-Q100 qualification not stated for this consumer/industrial MPU - consult ST official compliance documentation for certificates.
