WGI210IS - Intel I210-IS Gigabit Ethernet Controller QFN-64
MPN: WGI210IS ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
WGI210IS Overview
Background knowledge: A Gigabit Ethernet controller is an interface IC that connects a host processor to a copper or fiber Ethernet link, handling PHY encoding/decoding, MAC framing, DMA, and PCIe transaction-layer services. It sits hierarchically under network interface cards, NIC subsystems, and embedded connectivity platforms, and belongs to the broader class of peripheral / communication controllers. Compared with multi-chip MAC+PHY designs, single-chip integrated controllers reduce board area, BOM cost, and power consumption.
Key features include support for IEEE 802.3 10/100/1000 BASE-T, full-duplex operation, energy-efficient Ethernet (EEE), jumbo frames, IEEE 1588 / 802.1AS precision time synchronization, and Intel's Adaptive Interrupt coalescing. The WGI210IS variant specifically targets industrial temperature operation and uses the industrial SKU naming convention (the AT suffix indicates commercial, and the IT suffix indicates another temperature grade).
Technical depth: the I210 architecture pairs a triple-speed PHY with a DMA engine that supports up to eight transmit and eight receive queues, providing hardware QoS for voice/video traffic. Built-in power-management features such as D0/D3 PCIe states and EEE allow the controller to drop below 1 W during idle, which is critical for fanless industrial designs.
Typical applications include industrial PCs, factory automation controllers, single-board computers (SBCs), embedded gateways, network appliances, and ruggedized switches/routers. The PCIe v2.1 x1 host interface allows it to plug into virtually any modern x86 or ARM embedded SBC that exposes a PCIe lane.
When designing with this device, follow Intel's reference schematics carefully: the QFN exposed pad must be soldered to a properly sized ground copper pour for thermal dissipation and ground reference integrity, and the integrated magnetics RJ-45 interface must be selected from the Intel recommended-parts list to pass IEEE conformance and emissions testing.
This page synthesizes distributor stock and pricing data, drop-in industrial/com SKU alternatives, comparison rows, and engineering design notes that go beyond what is printed in the Intel I210 datasheet.
Drop-in alternatives for WGI210IS — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with WGI210IS (same form factor and footprint) — differing in Host Interface, Jumbo Frame Support, Package, Product Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
WGI210AT
✅ Drop-In✓ In Stock
$8.45 / Unit
View Datasheet →WGI210IT
✅ Drop-In📋 Reference alternative (not in catalog)
WGI210ATSLJXQ
✅ Drop-In📋 Reference alternative (not in catalog)
WGI210ATSLJXR
✅ Drop-In📋 Reference alternative (not in catalog)
WGI218V S LK3D
✅ Drop-In📋 Reference alternative (not in catalog)
WGI217V S LJWG
✅ Drop-In📋 Reference alternative (not in catalog)
WGI210IS Specifications
| Product Type | Gigabit Ethernet Controller (single-chip MAC+PHY+PCIe) |
| Host Interface | PCI Express v2.1 (2.5 GT/s) |
| Network Interface | 10/100/1000 Mbps (IEEE 802.3) |
| LAN Interface | Copper, integrated tri-speed PHY |
| Supply Voltage | 0.9 V / 3.3 V |
| Operating Modes | Full-duplex, Half-duplex |
| Package | 64-pin QFN EP, 9 mm x 9 mm |
| Mounting Type | Surface Mount |
| Technology | CMOS |
| Protocol Support | IEEE 802.3, IEEE 1588 / 802.1AS |
| Jumbo Frame Support | Yes (up to 9.5 KB) |
| Energy Efficient Ethernet | Yes (EEE 802.3az) |
| Wake-on-LAN | Yes (WoL) |
| RoHS Status | Compliant |
WGI210IS Pin Configuration
| Pin 1 | VDD_0P9 — 0.9 V core supply |
| Pin 2 | VDD_0P9 — 0.9 V core supply |
| Pin 3 | VSS — Ground |
| Pin 4 | PETp0 — PCIe transmit differential pair, lane 0 (+) |
| Pin 5 | PETn0 — PCIe transmit differential pair, lane 0 (-) |
| Pin 6 | VSS — Ground |
| Pin 7 | PERp0 — PCIe receive differential pair, lane 0 (+) |
| Pin 8 | PERn0 — PCIe receive differential pair, lane 0 (-) |
| Pin 9 | VSS — Ground |
| Pin 10 | REF_CLK_P — PCIe reference clock (+) |
| Pin 11 | REF_CLK_N — PCIe reference clock (-) |
| Pin 12 | VSS — Ground |
| Pin 13 | PERSTn — PCIe fundamental reset (active low) |
| Pin 14 | WAKE_n — Wake signal for WAKE# to host |
| Pin 15 | JTAG_TCK — JTAG test clock |
| Pin 16 | JTAG_TDO — JTAG test data out |
| Pin 17 | JTAG_TMS — JTAG test mode select |
| Pin 18 | JTAG_TDI — JTAG test data in |
| Pin 19 | JTAG_TRST_n — JTAG test reset (active low) |
| Pin 20 | VDD_3P3 — 3.3 V I/O supply |
| Pin 21 | VDD_3P3 — 3.3 V I/O supply |
| Pin 22 | VSS — Ground |
| Pin 23 | LED0 — Activity/link LED output 0 |
| Pin 24 | LED1 — Activity/link LED output 1 |
| Pin 25 | LED2 — Activity/link LED output 2 |
| Pin 26 | SMB_CLK — SMBus clock (management interface) |
| Pin 27 | SMB_DATA — SMBus data (management interface) |
| Pin 28 | SMB_ALRT_n — SMBus alert (active low) |
| Pin 29 | NC — Not connected (per datasheet) |
| Pin 30 | NC — Not connected (per datasheet) |
| Pin 31 | EEPROM_CS — SPI/EEPROM chip select |
| Pin 32 | EEPROM_SK — SPI/EEPROM serial clock |
| Pin 33 | EEPROM_DI — SPI/EEPROM data in |
| Pin 34 | EEPROM_DO — SPI/EEPROM data out |
| Pin 35 | VSS — Ground |
| Pin 36 | MDI0P — Media-dependent interface, pair 0 (+) |
| Pin 37 | MDI0N — Media-dependent interface, pair 0 (-) |
| Pin 38 | MDI1P — Media-dependent interface, pair 1 (+) |
| Pin 39 | MDI1N — Media-dependent interface, pair 1 (-) |
| Pin 40 | MDI2P — Media-dependent interface, pair 2 (+) |
| Pin 41 | MDI2N — Media-dependent interface, pair 2 (-) |
| Pin 42 | MDI3P — Media-dependent interface, pair 3 (+) |
| Pin 43 | MDI3N — Media-dependent interface, pair 3 (-) |
| Pin 44 | VSS — Ground |
| Pin 45 | AVDD_0P9 — Analog 0.9 V supply (PHY) |
| Pin 46 | AVDD_1P1 — Analog 1.1 V supply (PHY) |
| Pin 47 | AVDD_3P3 — Analog 3.3 V supply (PHY) |
| Pin 48 | VSS — Ground |
| Pin 49 | RSET — PHY bias resistor (connect to ground via 4.99 kΩ) |
| Pin 50 | XTAL_IN — 25 MHz crystal input |
| Pin 51 | XTAL_OUT — 25 MHz crystal output |
| Pin 52 | VSS — Ground |
| Pin 53 | LAN_PWR_GOOD — LAN power good input |
| Pin 54 | MAIN_PWR_GOOD — Main power good input |
| Pin 55 | AUX_PWR — Auxiliary power presence |
| Pin 56 | VSS — Ground |
| Pin 57 | VDD_0P9 — 0.9 V core supply |
| Pin 58 | VDD_0P9 — 0.9 V core supply |
| Pin 59 | VDD_3P3 — 3.3 V I/O supply |
| Pin 60 | VDD_3P3 — 3.3 V I/O supply |
| Pin 61 | VSS — Ground |
| Pin 62 | POR_BYP — POR bypass / test pin |
| Pin 63 | NC — Not connected (per datasheet) |
| Pin 64 | NC — Not connected (per datasheet) |
Typical Applications
WGI210IS is suitable for 7 applications: Industrial PCs (IPC) and Embedded SBCs, Factory Automation Controllers (PLCs, Edge Gateways), Network Appliances and Small-Business Routers, Single-Board Computers and Developer Kits, Server and Storage Add-In Cards (LOM/OCP NICs), Industrial IoT Gateways and Edge Compute Nodes, Medical and Diagnostic Imaging Equipment.
Industrial PCs (IPC) and Embedded SBCs
The WGI210IS fits industrial PC and SBC platforms because its PCIe v2.1 (2.5 GT/s) x1 host interface plugs directly into the standard FIP riser or M.2/PCIe slot exposed by x86 and ARM SBCs. Its industrial-temperature grade and CMOS integration make it reliable across -40 C to +85 C factory-floor environments without thermal throttling. With 8 TX/8 RX DMA queues and IEEE 1588/802.1AS precision time synchronization, it can sustain deterministic real-time traffic alongside general IT data on the same link, eliminating the need for a discrete TSN controller. Place it between the SoC PCIe lane and the integrated magnetics RJ-45 connector from the Intel recommended-parts list, then run the Intel-provided NVM/EFI driver image from the onboard SPI flash.
Recommended
Factory Automation Controllers (PLCs, Edge Gateways)
In factory automation, the WGI210IS provides a single Gigabit Ethernet port for EtherNet/IP, PROFINET, and Modbus TCP convergence on the same physical link. The PCIe v2.1 host interface allows the controller to be added to a small industrial gateway without consuming a second Ethernet MAC on the host SoC. Energy Efficient Ethernet (IEEE 802.3az) keeps idle link power below 1 W, important for fanless DIN-rail enclosures. Use the WGI210IS between the host ARM SoC and a galvanically-isolated RJ-45 jack, with the eFuse/TPS25942ARVCT guarding the upstream 3.3 V rail during hot-plug events on the factory floor.
Recommended
Network Appliances and Small-Business Routers
The WGI210IS suits small-business router, firewall, and UTM appliances that already expose a PCIe lane on the host CPU. Its GbE throughput with hardware QoS (8 TX/8 RX queues) handles gigabit WAN traffic while keeping CPU utilization low, a measurable advantage over USB-based GbE bridges. The 64-pin QFN exposed pad provides the thermal headroom needed for sustained gigabit operation without a heatsink. Pair it with a GbE PHY magnetics module from the Intel recommended-parts list, route the PCIe x1 differential pair with 90 ohm impedance, and validate the IEEE 802.3 conformance with the Intel Ethernet toolkit.
Recommended
Single-Board Computers and Developer Kits
On Raspberry-Pi-class and x86 SBC kits, the WGI210IS adds a second Gigabit Ethernet port via the PCIe lane exposed on the carrier board. The QFN-64 footprint simplifies carrier design because the BOM is shared with the Intel reference design and Intel provides NVM/EFI driver binaries for Linux and Windows. Its single-chip MAC+PHY+SerDes integration eliminates the magnetics external to the RJ-45 jack and reduces the carrier BOM by roughly 30 percent versus discrete MAC+PHY designs. Mount it next to the RJ-45 jack with a 4-layer PCB and a continuous ground pour stitched around the high-speed traces.
Recommended
Server and Storage Add-In Cards (LOM/OCP NICs)
The WGI210IS is used on LOM (LAN on Motherboard) and OCP-style network add-in cards where its PCIe v2.1 x1 host interface fits into standard NIC edge connectors and its GbE throughput handles 1 Gbps link aggregation with minimal CPU offload. With 8 TX/8 RX queues, RSS hashing, and SR-IOV virtualization support, it is well-suited to hypervisor-host NIC roles in light-scale servers and storage appliances. Place it on a 4-layer NIC PCB with 90 ohm PCIe traces, follow the Intel reference stack-up, and validate with the Intel iSCSI/FCoE/DPDK driver stack.
Recommended
Industrial IoT Gateways and Edge Compute Nodes
The WGI210IS fits edge-compute and IIoT gateway designs where deterministic GbE connectivity is required alongside wireless (LTE/5G) uplink. Its PCIe v2.1 host interface allows the GbE port to be added without consuming the SoC's embedded MAC, freeing the SoC Ethernet port for TSN or wireless backhaul. Industrial-temperature qualification supports outdoor enclosures and factory cabinets. Pair it with an RJ-45 jack with integrated PoE-PD support if the gateway must be powered over the cable, then run the Intel Ethernet NVM image from the on-board SPI flash.
Recommended
Medical and Diagnostic Imaging Equipment
The WGI210IS serves medical imaging and diagnostic equipment where stable GbE connectivity to DICOM/PACS archives is required under IEC 60601-1 EMI/EMC constraints. Its CMOS integration and low idle power reduce thermal footprint inside sealed enclosures, and the industrial-temperature grade covers clinical-environment ranges. Use it with a fully isolated, medical-grade RJ-45 jack, validate EMI/EMC per IEC 60601-1, and pair it with a watchdog supervisor (TPS3700DDCR) on the 3.3 V rail to detect brown-out conditions during imaging acquisition.
Recommended
Recommended Products Summary
Engineering reference data for WGI210IS — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | WGI210AT | WGI210IT | WGI210ATSLJXQ | WGI210ATSLJXR | WGI218V S LK3D | WGI217V S LJWG |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | QFN-64 (9x9 mm) | QFN-64 (9x9 mm) - same | QFN-64 (9x9 mm) - same | QFN-64 (9x9 mm) - same | QFN-64 (9x9 mm) - same | QFN-64 (9x9 mm) - same | QFN-64 (9x9 mm) - same |
| Host Interface | PCIe v2.1 (2.5 GT/s) | PCIe v2.1 (2.5 GT/s) | PCIe v2.1 (2.5 GT/s) | PCIe v2.1 (2.5 GT/s) | PCIe v2.1 (2.5 GT/s) | PCIe (similar GbE controller family) | PCIe (older I217 GbE controller family) |
| Ethernet Speeds | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps |
Key Differentiators
- Industrial-temperature grade SKU (vs WGI210AT)
- Cross-compatible industrial-temperature SKU within the same family (vs WGI210IT)
- Higher GbE silicon generation than older I217 family (vs WGI217V S LJWG)
Design Notes
PCIe x1 differential pairs (PETp0/PETn0, PERp0/PERn0) must be routed as 90 ohm differential impedance on the top layer over a continuous ground reference plane. Maintain 100 ohm common-mode tolerance, keep intra-pair skew below 5 mils, and isolate the pair from switching power and clock traces. The exposed thermal pad must be soldered to a ground copper pour of at least 1 square inch for thermal dissipation and reference integrity. Length-matching between PCIe REF_CLK and PCIe data lines must follow the Intel reference layout in the I210 datasheet.
The WGI210IS requires a clean dual-rail supply: 0.9 V (analog + digital core) and 3.3 V (I/O + analog PHY). Place 10 uF + 0.1 uF ceramic decoupling capacitors within 50 mils of each VDD pin, and a 4.7 uF bulk capacitor at the AVDD pins. Use a low-noise LDO (e.g., TPS7A7002DDA or equivalent) on the analog rail to meet the PHY SNR mask. Power-good sequencing must ensure 0.9 V rises before 3.3 V, or follow the Intel reference power-on sequence to avoid latch-up at start-up.
Do not omit the 25 MHz crystal on XTAL_IN/XTAL_OUT - the I210 requires an external crystal reference; the internal PHY uses this as its base baud clock. Do not skip EEPROM programming - the WGI210IS requires an external SPI EEPROM with the Intel NVM image for MAC address, PCIe configuration, and LED behavior; without it the controller does not enumerate on the PCIe bus. Also avoid routing the MDI traces over power-plane splits, which couple common-mode noise into the PHY and degrade 1000BASE-T link margin.
Although the I210 silicon is designed for low-power operation, sustained gigabit traffic at elevated temperature can drive junction temperature above 100 C if the PCB does not provide adequate copper heatsinking. The QFN-64 EP package dissipates roughly 0.7 W to 1.2 W under full gigabit load. Add a 4-layer PCB with a continuous top-layer ground pour stitched to the EP for thermal spreading, and validate with a thermal probe at the EP center during sustained traffic at the worst-case ambient.
MDI differential pairs (MDI0P/N through MDI3P/N) must be routed as 100 ohm differential impedance with intra-pair skew below 2 mils and inter-pair length matching within 50 mils. Place the integrated magnetics RJ-45 jack within 25 mm of the MDI pins to meet IEEE 802.3 return-loss and mode-conversion masks. Use the Intel recommended-parts list for the magnetics module to pass IEEE conformance and emissions testing; non-qualified magnetics can degrade link margin by 3-5 dB.
Compliance Information
RoHS and REACH compliance per Arrow Electronics product listing. Halogen-free per Intel product page. Industrial-temperature SKU suitable for ruggedized applications; not AEC-Q100 qualified (not an automotive part).
