10AS066K2F35I2SG - Arria 10 SX SoC FPGA, 660K LE | Intel
N.º da peça: 10AS066K2F35I2SG ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $7184.52 | $7.184,52 |
| 10 | $6950 | $69.500,00 |
| 100 | $6500 | $650.000,00 |
| 500 | $6100 | $3.050.000,00 |
| 1.000 | $5750 | $5.750.000,00 |
10AS066K2F35I2SG Visão geral
An SoC FPGA combines a hard processor subsystem with programmable logic on a single die, enabling deterministic real-time control alongside flexible hardware acceleration. The Arria 10 SX sits in the SoC hierarchy below Stratix 10 and above Cyclone V, balancing mid-range FPGA fabric density with a Cortex-A9 application processor cluster suitable for Linux and real-time operating system workloads. The hard ARM cores offload host-side tasks from the FPGA fabric, eliminating soft-processor overhead in embedded platforms.
Key features include 660K logic elements, embedded DSP blocks for fixed- and floating-point acceleration, embedded transceivers for high-speed serial I/O, and shared coherent memory between the HPS and FPGA fabric. The Arria 10 SX device family supports LPDDR4, DDR4, and DDR3 external memory interfaces through hardened controllers, and integrates CoreSight debug infrastructure for non-intrusive processor trace. The 20 nm process node balances static power and performance for industrial-grade deployments.
Typical applications include industrial motor control, video broadcast processing, military radar front-end pre-processing, and 5G baseband prototyping. The integrated Cortex-A9 subsystem runs Linux, VxWorks, or RTOS workloads while the FPGA fabric handles deterministic DSP pipelines, custom peripherals, and high-bandwidth memory interfaces.
When designing with this device, plan the HPS-to-FPGA bridge topology early - AXI bus widths and arbitration policies impact sustained throughput. Pin assignments must respect the dedicated HPS ball locations, which differ from the general-purpose FPGA I/O bank rules.
This page synthesizes distributor pricing, drop-in same-package Arria 10 SX variants, and practical design notes for the 10AS066K2F35I2SG not found in the standalone manufacturer datasheet.
Alternativas drop-in para 10AS066K2F35I2SG — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com 10AS066K2F35I2SG (mesmo formato e footprint) — diferindo em Package, Speed Grade, Logic Elements, Mounting Type, RoHS Status.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
10AS066K2F35I2LG
✅ Drop-In✓ Em estoque
$5650.15 / unidade
Ver ficha técnica →10AS066K2F35E2SG
✅ Drop-In✓ Em estoque
$2890 / unidade
Ver ficha técnica →10AS066K2F35E2LG
✅ Drop-In✓ Em estoque
$3360 / unidade
Ver ficha técnica →10AS066K2F35E1HG
✅ Drop-In✓ Em estoque
$3290 / unidade
Ver ficha técnica →10AS066K1F35I1HG
✅ Drop-In✓ Em estoque
$2275 / unidade
Ver ficha técnica →10AS057K2F35I2SG
✅ Drop-In✓ Em estoque
$3198.4 / unidade
Ver ficha técnica →10AS066K2F35I2SG Classificações máximas e características elétricas
| Product Family | Arria 10 SX SoC FPGA |
| Logic Elements | 660,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Core Clock | 1.5 GHz |
| Encapsulamento | 1152-ball FCBGA (35x35 mm) |
| Temperature Grade | Industrial (-40C to +100C) |
| Speed Grade | 2 (mid-tier) |
| Process Node | 20 nm TSMC |
| Tipo de montagem | Surface Mount |
| Status RoHS | Compliant |
| GPIO | 396 user I/O |
| Device Variant | 10AS066K2F35 |
Guia de Configuração de Pinos do 10AS066K2F35I2SG 1152-ball fcbga (35x35 mm)
Configuração de pinos para 10AS066K2F35I2SG (pacote 1152-ball fcbga (35x35 mm)). Este CI digital inclui GPIO, interfaces de comunicação (UART, SPI, I2C) e pinos de alimentação. Consulte o datasheet do fabricante para funções alternativas dos pinos e opções de configuração. Essencial para projeto de sistemas embarcados e layout de PCB.
Nenhum dado detalhado de pinagem disponível para 10AS066K2F35I2SG.
Consulte a ficha técnica para a configuração completa dos pinos.
Aplicações típicas
10AS066K2F35I2SG é adequado para 6 aplicaçãos: Industrial Motor Control, Video Broadcast Processing, 5G Baseband Prototyping, Military Radar Front-End Pre-Processing, Medical Imaging Accelerator, Embedded Data Acquisition Platform.
Industrial Motor Control
The 10AS066K2F35I2SG fits industrial motor drives because its hard ARM Cortex-A9 cores handle HMI, commutation sequencing, and EtherCAT/CAN-FD host stacks while the 660K-logic-element FPGA fabric implements field-oriented control (FOC) and Sigma-Delta ADC interfaces. Its 1.5 GHz HPS clock, 20 nm process, and industrial temperature grade (-40C to +100C) deliver deterministic sub-microsecond control loops. Industrial-grade servo and variable-frequency drive designs rely on this combination of programmable logic and processor headroom.
Recomendado
Video Broadcast Processing
Broadcast video routers and 4K/UHD processing blades leverage the 10AS066K2F35I2SG's 660K logic elements and dedicated video DSP blocks to run multi-stream HEVC and JPEG2000 codecs in hardware. The dual ARM Cortex-A9 HPS manages networking stacks (SMPTE 2022, NDI, SMPTE 2110) and system telemetry. Industrial temperature grade and 1152-ball FCBGA package support sustained workload at elevated ambient temperatures typical of broadcast equipment racks.
Recomendado
5G Baseband Prototyping
5G New Radio prototyping platforms use the 10AS066K2F35I2SG for its high DSP block count and embedded transceivers, enabling real-time baseband processing including LDPC decoders and FFT pipelines. The Cortex-A9 HPS runs the physical-layer control software and link-adaptation logic, sharing coherent memory with the FPGA. Industrial temperature operation and the 1152-ball FCBGA package suit outdoor small-cell and macro-prototyping racks where thermal margins are critical.
Recomendado
Military Radar Front-End Pre-Processing
Phased-array and synthetic-aperture radar pre-processing cards use the 10AS066K2F35I2SG to implement pulse compression, MTI filtering, and beamforming in the FPGA fabric while the Cortex-A9 HPS runs tracker and display software. The industrial temperature grade and high logic density make it suitable for ruggedized enclosures and shipboard/airborne platforms. The integrated HPS eliminates the need for a separate processor card, reducing SWaP-C in defense applications.
Recomendado
Medical Imaging Accelerator
Ultrasound beamformers, CT reconstruction engines, and MRI pre-processors use the 10AS066K2F35I2SG to run real-time image reconstruction algorithms in dedicated FPGA hardware. The Cortex-A9 HPS manages the user interface, DICOM stack, and network interface, while shared LPDDR4 memory via the HPS-to-FPGA bridge keeps data movement fast. Industrial temperature operation and deterministic latency benefit diagnostic equipment used in hospital and field-deployable settings.
Recomendado
Embedded Data Acquisition Platform
High-channel-count data-acquisition and instrumentation platforms use the 10AS066K2F35I2SG to interface with multi-MHz ADC and DAC devices through FPGA LVDS I/O while running Linux control and analysis software on the HPS. Shared LPDDR4 memory sustains streaming bandwidth between fabric-acquired samples and host processing. Industrial temperature operation supports factory-floor, test-rig, and outdoor sensor installations.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para 10AS066K2F35I2SG — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | 10AS066K2F35I2LG | 10AS066K2F35E2SG | 10AS066K2F35E2LG | 10AS066K2F35E1HG | 10AS066K1F35I1HG | 10AS057K2F35I2SG |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-FCBGA (35x35 mm) | 1152-FCBGA (35x35 mm) - same | 1152-FCBGA (35x35 mm) - same | 1152-FCBGA (35x35 mm) - same | 1152-FCBGA (35x35 mm) - same | 1152-FCBGA (35x35 mm) - same | 1152-FCBGA (35x35 mm) - same |
| Logic Elements | 660K | 660K | 660K | 660K | 660K | 660K | 570K (-14%) |
| Speed Grade | 2 (mid-tier) | 2 | 2 | 2 | 1 (slower) | 1 (slower) | 2 |
| Temperature Grade | Industrial (-40C to +100C) | Industrial | Commercial (0C to +100C) | Commercial (0C to +100C) | Commercial (0C to +100C) | Industrial | Industrial |
| Packaging Format | Tray (SG) | Tape & Reel (LG) | Tray (SG) | Tape & Reel (LG) | Tape & Reel (HG) | Tape & Reel (HG) | Tray (SG) |
| Hard Processor System | Dual ARM Cortex-A9 + CoreSight | Dual ARM Cortex-A9 + CoreSight | Dual ARM Cortex-A9 + CoreSight | Dual ARM Cortex-A9 + CoreSight | Dual ARM Cortex-A9 + CoreSight | Dual ARM Cortex-A9 + CoreSight | Dual ARM Cortex-A9 + CoreSight |
| Maximum HPS Clock | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz |
Principais diferenciais
- Tray packaging format optimized for low-volume prototyping (vs 10AS066K2F35I2LG)
- Industrial temperature grade for harsh-environment deployments (vs 10AS066K2F35E2SG)
- Higher 660K logic-element density over smaller Arria 10 family members (vs 10AS057K2F35I2SG)
- Speed grade 2 balanced performance for industrial workloads (vs 10AS066K2F35E1HG)
Notas de projeto
The 1152-ball FCBGA (F35) package requires high-density PCB design with microvia stackups and 0.8 mm or finer ball pitch. Use the Intel Quartus Prime pin planner to assign HPS-dedicated balls (USB, EMAC, NAND, QSPI) before general-purpose I/O banks, since HPS balls have fixed locations. Decoupling: place 100 nF MLCCs under the package BGA shadow within 200 mils of every power pin, and bulk 10 uF-22 uF tantalum or polymer capacitors on each supply rail.
At industrial temperature grade (-40C to +100C), the Arria 10 SX FPGA fabric can draw significant dynamic current depending on clock rate and toggle activity. Use a thermal via array under the package center and tie the central ground balls to an inner plane. Static power scales with junction temperature; 20 nm Arria 10 worst-case junction can exceed 100C without airflow, so chassis airflow or a heat-spreader is required for full-performance designs.
Estimated power budgeting for 660K LE @ 70% utilization at 250 MHz toggle rate: roughly 4-7 W dynamic FPGA plus 1.5-3 W HPS. Total ~6-10 W continuous. Configure unused GPIO banks as tri-stated inputs with weak pull-ups, otherwise floating inputs cause leakage and excess current. Always assert CONFIG_DONE before enabling HPS release-from-reset to avoid HPS booting with uninitialized FPGA fabric.
DDR4/LPDDR4/DDR3 external memory interfaces routed from the HPS must follow the Intel pin-connection guidelines with matched trace lengths within the listed tolerance (typically +/- 25 mil for DDR4). Use the Quartus Prime memory controller IP with calibrated read/write leveling. Avoid routing the high-speed transceivers adjacent to switching power converter traces; keep at least 4x dielectric spacing between SERDES lanes and noisy signals.
Configure the configuration scheme (typically AS x4 or JTAG) before PCB layout, because dedicated configuration pins (MSEL, nCONFIG, nSTATUS) have fixed ball locations that differ from general-purpose I/O. If using Active Serial x4 for fast configuration from QSPI, ensure the QSPI device connects to the dedicated AS configuration pins per the Arria 10 configuration user guide.
Informações de conformidade
RoHS compliance inferred from trailing 'G' suffix in MPN per Intel Arria 10 ordering code conventions. REACH, halogen-free, and conflict-minerals declarations not explicitly stated in the verified web data; refer to Intel product compliance certificates for confirmation.
