10AS066K2F35E2SG - Arria 10 SX SoC FPGA, 660K LE, 1152-FBGA | Intel
MPN: 10AS066K2F35E2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4126.44 | $4,126.44 |
| 10 | $3820 | $38,200.00 |
| 100 | $3450 | $345,000.00 |
| 500 | $3120 | $1,560,000.00 |
| 1,000 | $2890 | $2,890,000.00 |
Drop-in alternatives for 10AS066K2F35E2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AS066K2F35E2LG
✅ Drop-In✓ In Stock
$3360 / Unit
View Datasheet →10AS066K2F35E1HG
✅ Drop-In✓ In Stock
$3290 / Unit
View Datasheet →10AS066K1F35E1HG
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →10AS048K2F35E2SG
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Contact for price
View Datasheet →10AS066H4F34I3SG
✅ Drop-In✓ In Stock
$2295 / Unit
View Datasheet →10AS066K2F35E2SG Maximum Ratings & Electrical Characteristics
| Series | Arria 10 SX |
| Family | Arria 10 SX SoC FPGA |
| Logic Elements | 660,000 |
| Process Technology | 20 nm |
| Core Voltage | 0.9 V |
| DSP Performance | Up to 1.5 GHz (variable-precision DSP) |
| HPS CPU Cores | Dual ARM Cortex-A9 MPCore |
| HPS Debug | CoreSight |
| User I/O | 396 |
| Package | 1152-ball FC-FBGA (F35), 35 x 35 mm |
| Speed Grade | -2 (E2 industrial, slower timing corner) |
| Operating Temperature | Industrial grade (per E2 suffix) |
| Mounting Type | Surface Mount (flip-chip BGA) |
| RoHS Status | Compliant (per distributor listing) |
10AS066K2F35E2SG 1152-ball fc-fbga (f35), 35 x 35 mm Pin Configuration Guide
Complete pinout information for 10AS066K2F35E2SG (1152-ball fc-fbga (f35), 35 x 35 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS066K2F35E2SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS066K2F35E2SG is suitable for 6 applications: Wireless Baseband Processing, Military Radar Signal Processing, Industrial Machine Vision, Broadcast Video Processing, Test and Measurement Equipment, Medical Imaging (Ultrasound / CT).
Wireless Baseband Processing
The 10AS066K2F35E2SG is well suited to wireless baseband processing because its 660K logic elements and variable-precision DSP blocks running up to 1.5 GHz deliver the throughput required for LTE and 5G NR channel decoding, FFT/iFFT kernels, and crest-factor reduction. The dual Cortex-A9 MPCore HPS runs the protocol stack, RRM, and MAC scheduler, while the FPGA fabric accelerates the PHY datapath, keeping deterministic latency on the time-critical path. The 1152-ball F35 package supports up to 14.1 Gbps transceiver channels for CPRI and JESD204B backhaul links, and the -E2 speed grade provides industrial temperature margin for outdoor base-station deployments.
Recommended
Military Radar Signal Processing
The 10AS066K2F35E2SG fits military radar signal processing workloads because its 1.5 GHz floating-point DSP blocks perform pulse compression, MTI filtering, and beamforming kernels with deterministic throughput. The 660K logic elements provide parallel datapath density for phased-array calibration, while the integrated Cortex-A9 HPS handles tracking, classification, and network interfaces. The 1152-FBGA F35 footprint with -E2 industrial speed grade supports ruggedized enclosures with extended temperature operation, and the on-chip hard memory controllers feed DDR3/DDR4 buffers directly to DSP blocks for low-latency sample processing.
Recommended
Industrial Machine Vision
The 10AS066K2F35E2SG is appropriate for industrial machine vision systems because its programmable fabric accelerates image preprocessing, defect detection, and convolutional inference, while the dual-core Cortex-A9 HPS runs the application layer, PLC communication, and HMI. The 396 user I/O support multi-camera aggregation through LVDS, MIPI CSI-2, or GigE Vision bridges, and the integrated CoreSight debug infrastructure simplifies firmware bring-up. The -E2 industrial speed grade and 35 x 35 mm FC-FBGA package fit factory-floor enclosures where ambient temperatures can rise and vibration tolerance matters.
Recommended
Broadcast Video Processing
The 10AS066K2F35E2SG fits broadcast video processing because its DSP blocks handle 4K/UHD HEVC and AVC decode/encode pipelines, and its FPGA fabric accelerates color-space conversion, deinterlacing, and frame-rate conversion in real time. The 396 user I/O accept SDI, HDMI, and DisplayPort inputs via FPGA IP, while the Cortex-A9 HPS runs the device control plane, network management, and firmware updates. The 1152-ball F35 package supports multi-transceiver operation for SMPTE ST 2110 IP-based broadcast workflows, and the -E2 speed grade delivers reliable operation in 24/7 broadcast equipment racks.
Recommended
Test and Measurement Equipment
The 10AS066K2F35E2SG is suited to high-end test and measurement equipment such as oscilloscopes, signal analyzers, and protocol testers because its 1.5 GHz DSP blocks implement real-time FFT, digital downconversion, and trigger-decision logic. The dual-core HPS runs the user interface, SCPI command parser, and LAN connectivity, while the FPGA fabric handles sample acquisition and parallel DSP. The 14.1 Gbps transceivers interface to high-speed ADCs and DACs via JESD204B/C, and the -E2 industrial speed grade ensures calibration stability across lab and field environments.
Recommended
Medical Imaging (Ultrasound / CT)
The 10AS066K2F35E2SG suits medical imaging systems because its variable-precision DSP blocks perform beamforming, image reconstruction, and Doppler processing for ultrasound or CT front-end electronics. The Cortex-A9 HPS handles the patient interface, DICOM networking, and display pipeline, while the FPGA fabric ensures deterministic latency on the real-time imaging path. The 1152-ball F35 package and -E2 industrial speed grade fit medical equipment where reliability, thermal stability, and regulatory compliance drive design decisions, with 396 user I/O supporting multi-channel transducer arrays.
Recommended
Recommended Products Summary
Engineering reference data for 10AS066K2F35E2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS066K2F35E2LG | 10AS066K2F35E1HG | 10AS066K1F35E1HG | 10AS048K2F35E2SG | 10AS066H4F34I3SG |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-FBGA F35 (35x35 mm) | 1152-FBGA F35 (same) | 1152-FBGA F35 (same) | 1152-FBGA F35 (same) | 1152-FBGA F35 (same) | 1152-FBGA F34 (verify mechanical compatibility) |
| Logic Elements | 660,000 | 660,000 | 660,000 | 660,000 | 480,000 | 660,000 |
| Speed Grade | -E2 industrial (slower) | -E2 industrial | -E1 industrial (faster) | -E1 industrial (faster) | -E2 industrial | -I3 industrial |
| HPS Cores | Dual Cortex-A9 | Dual Cortex-A9 | Dual Cortex-A9 | Dual Cortex-A9 | Dual Cortex-A9 | Dual Cortex-A9 |
| DSP Performance | Up to 1.5 GHz | Up to 1.5 GHz | Up to 1.5 GHz | Up to 1.5 GHz | Up to 1.5 GHz | Up to 1.5 GHz |
| Process Technology | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm |
| Core Voltage | 0.9 V | 0.9 V | 0.9 V | 0.9 V | 0.9 V | 0.9 V |
| User I/O | 396 | 396 | 396 | 396 | 396 | [DATA_NEEDED] |
Key Differentiators
- Lower dynamic power from -E2 speed grade (vs 10AS066K2F35E1HG)
- Higher logic-element density than 480K variant (vs 10AS048K2F35E2SG)
- Drop-in lead-free alternative available (vs 10AS066K2F35E2LG)
Design Notes
The 1152-ball FC-FBGA F35 package measures 35 x 35 mm and requires a high-layer-count PCB (typically 12+ layers) with microvia stack-ups to fan out from the 1.0 mm ball pitch. Use Intel's recommended land pattern and via-in-pad or dog-bone fan-out per the Arria 10 device handbook PCB chapter. Match-length impedance-controlled routing is mandatory for DDR3/DDR4 interfaces and for 14.1 Gbps transceiver channels, with reference stack-ups available from Intel's board design resource center.
Estimated: at full fabric utilization and 1.5 GHz DSP activity, the 10AS066K2F35E2SG may dissipate 15 to 25 W, requiring a heatsink plus thermal interface material or top-side cold plate. Place NTC thermistors near the package center to monitor junction temperature, and follow Intel's PowerTree guidelines for sequencing the 0.9 V core rail before transceiver and I/O supplies. Use the Quartus Prime PowerPlay analyzer to estimate dynamic power per design block before committing to the thermal solution.
Do not substitute a -E2 speed grade part for a -I3 or -E3 grade design without re-running timing closure in Quartus Prime, because the speed grade shift of approximately 10 to 15 percent Fmax per step can break critical paths. Confirm the K1 versus K2 silicon-variant ordering code matches the datasheet expected for your transceiver PLL configuration, and verify transceiver channel count against the variant's resource table before PCB layout.
For 14.1 Gbps transceiver channels, follow Intel's Transceiver Link Design guidelines for pre-emphasis, equalization, and PCB material selection (typically Megtron 6 or equivalent low-loss dielectric). Maintain 100 ohm differential impedance on transceiver pairs and keep stubs shorter than 150 mil to preserve signal integrity. Use IBIS-AMI models for system-level channel simulation before fabrication.
Compliance Information
RoHS compliance per distributor listing. Industrial grade E2 suffix, not AEC-Q100 qualified. Specific REACH, halogen-free, and conflict-mineral status not provided in source data; verify with Intel product compliance documentation for production qualification.
