10AS066K2F35E1HG - Arria 10 SX SoC FPGA, 660K LE, 1152-FBGA | Altera
MPN: 10AS066K2F35E1HG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4250 | $4,250.00 |
| 10 | $3990 | $39,900.00 |
| 50 | $3750 | $187,500.00 |
| 100 | $3520 | $352,000.00 |
| 500 | $3290 | $1,645,000.00 |
Drop-in alternatives for 10AS066K2F35E1HG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AS066K2F35I1HG
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10AS066K1F35E1HG
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View Datasheet →10AS066K1F35I1HG
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$2275 / Unit
View Datasheet →10AS066K2F35E1HG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 SX SoC FPGA |
| Logic Elements | 660,000 (660K) |
| Hard Processor Subsystem (HPS) | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Clock Frequency | 1.5 GHz |
| Package | 1152-FBGA, FC (35x35 mm) |
| Process Node | 20 nm |
| Speed Grade | -1 (industrial) |
| Temperature Grade | E (extended) |
| Transceivers | Up to 17.4 Gbps (multi-gigabit) |
| DSP Blocks | Variable-precision, hardened floating-point |
| Memory Interfaces | Hardened DDR3/DDR4 controllers |
| PCIe Hard IP | PCI Express Gen3 hard IP blocks |
| RoHS Status | Compliant |
| Mounting Type | Surface Mount (FCBGA) |
| Lead-Free | Yes |
10AS066K2F35E1HG 1152-fbga, fc (35x35 mm) Pin Configuration Guide
Complete pinout information for 10AS066K2F35E1HG (1152-fbga, fc (35x35 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS066K2F35E1HG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS066K2F35E1HG is suitable for 6 applications: Wireless Baseband Processing, Radar and Electronic Warfare Signal Chains, Broadcast Video Processing, High-Speed Serial Protocol Bridging, Medical Imaging Pre-Processing, Industrial Automation and Vision.
Wireless Baseband Processing
The 10AS066K2F35E1HG fits wireless baseband cards where its 660K logic elements implement channel cards while the dual 1.5 GHz ARM Cortex-A9 MPCore HPS runs the PHY control stack. Placed between antenna interfaces and the backhaul, it provides 24 multi-gigabit transceivers at up to 17.4 Gbps for CPRI or OBSAI fronthaul, plus hardened PCIe Gen3 IP for backhaul. The 17.4 Gbps transceivers and DSP blocks enable LTE/5G NR FFT and FEC offload. Unlike a pure ASIC, the FPGA fabric accelerates protocol upgrades without re-spin.
Recommended
Radar and Electronic Warfare Signal Chains
The 10AS066K2F35E1HG suits radar receiver/exciter designs where its hardened variable-precision DSP with floating-point assist performs pulse compression and FFT at sustained rates. With 660K LE the device implements multi-channel beamforming, while the dual 1.5 GHz Cortex-A9 HPS handles scheduling and tracking algorithms. The K2 transceiver tier supplies 24 channels of 17.4 Gbps serial link to ADCs/DACs and to neighbouring antenna cards. Its hardened PCIe Gen3 IP streams processed tracks to a host mission computer.
Recommended
Broadcast Video Processing
The 10AS066K2F35E1HG supports 4K/UHD broadcast pipelines where its 660K LE fabric runs multi-stream HEVC/H.264 encode-decode, color conversion, and graphics overlay in parallel. The dual 1.5 GHz ARM Cortex-A9 HPS hosts a Linux control plane with file ingest and stream management. Its 24 multi-gigabit transceivers provide SDI (SMPTE 2022/2082), HDMI 2.0, and 12G-SDI connectivity. Compared with merchant video SoCs, the FPGA fabric accelerates codec upgrades and custom watermarking without re-spin.
Recommended
High-Speed Serial Protocol Bridging
The 10AS066K2F35E1HG serves as a multi-protocol bridge converting PCIe Gen3, 10/40 GbE, SATA, and CPRI traffic on a single board. With 24 transceivers at 17.4 Gbps, the device aggregates lanes from multiple physical interfaces and presents a unified logical endpoint. The dual Cortex-A9 HPS at 1.5 GHz handles slow-path control while the 660K LE fabric implements cut-through switching and DMA. Hardened PCIe Gen3 blocks eliminate soft-IP resource overhead and simplify timing closure.
Recommended
Medical Imaging Pre-Processing
The 10AS066K2F35E1HG accelerates CT, MRI, and ultrasound front-ends where its variable-precision DSP and floating-point blocks perform back-projection, beamforming, and noise filtering in real time. The dual 1.5 GHz Cortex-A9 HPS runs the patient interface and DICOM stack while the 660K LE fabric accelerates the inner imaging loop. Its 17.4 Gbps transceivers connect to high-channel-count ADCs at the probe head. The SoC architecture lets the device replace separate CPU + FPGA + DSP boards.
Recommended
Industrial Automation and Vision
The 10AS066K2F35E1HG suits factory-automation vision and motion controllers where its dual 1.5 GHz ARM Cortex-A9 HPS runs deterministic EtherCAT or PROFINET masters while the 660K LE fabric accelerates machine-vision pipelines (edge detection, classification, defect inspection). The hardened PCIe Gen3 IP connects to host SCADA systems and 24 transceivers link multi-gigabit camera interfaces. Compared with discrete MCU + GPU stacks, the SoC FPGA reduces BOM, latency, and PCB footprint.
Recommended
Recommended Products Summary
Engineering reference data for 10AS066K2F35E1HG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS066K2F35I1HG | 10AS066K1F35E1HG | 10AS066K1F35I1HG |
|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 1152-FBGA, FC (35x35) | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same |
| Logic Elements | 660K | 660K | 660K | 660K |
| HPS | Dual Cortex-A9 @ 1.5 GHz | Dual Cortex-A9 @ 1.5 GHz | Dual Cortex-A9 @ 1.5 GHz | Dual Cortex-A9 @ 1.5 GHz |
| Transceiver Configuration | K2 (24 channels) | K2 (24 channels) | K1 (12 channels) | K1 (12 channels) |
| Max Transceiver Rate | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps |
| Temperature Grade | E (extended) | I (industrial) | E (extended) | I (industrial) |
| Hardened PCIe Gen3 IP | Yes | Yes | Yes | Yes |
Key Differentiators
- K2 transceiver configuration with 24 channels (vs 10AS066K1F35E1HG)
- Extended (E) temperature grade cost optimization (vs 10AS066K2F35I1HG)
- Hardened PCIe Gen3 IP blocks (vs 10AS048H1F34I1HG)
Design Notes
The 1152-FBGA F35 package requires a high-density PCB stack-up with 1-2-1 or 1-2-3-2-1 microvia layers for signal breakout. Use laser-drilled microvias under the BGA balls and standard through-vias on outer breakout layers. Decoupling per Intel/Altera pin connection guidelines: 0.1 uF + 1 uF + 10 uF per power rail as close to the package as possible. Maintain continuous ground return beneath the BGA for signal integrity.
At industrial E grade, the 10AS066K2F35E1HG is rated for junction temperatures up to 100C. Estimated power dissipation at full fabric utilization plus active HPS is typically 15-25 W. Provide a heat spreader or heatsink with at least 4 C/W thermal resistance and ensure PCB inner copper planes are stitched with thermal vias to the top-side spreader. Airflow at 1-2 m/s is recommended in enclosed chassis.
Do not confuse the F35 designator (1152-FBGA) with F34 or F29 packages from other Arria 10 SKUs. The 10AS066K2F35E1HG and 10AS048E2F29I1HG are NOT pin-compatible despite sharing part-number prefix 10AS. Always verify the package code on the Altera ordering part number page before laying out a new PCB or sourcing alternatives.
Differential transceiver channels require length-matched routing within 0.127 mm tolerance to meet 17.4 Gbps eye-mask. Use a 100-ohm differential stack-up with ground reference plane immediately beneath the traces. AC-coupling capacitors must be placed close to the receiver pins and rated for 6 GHz+ bandwidth to avoid attenuating 17.4 Gbps signals.
Compliance Information
RoHS and REACH compliant per Altera/Intel product page. Not AEC-Q100 qualified (industrial-grade FPGAs are typically AEC-Q100 only in dedicated auto part numbers).
