10AS066K1F35I1HG - Arria 10 SX SoC FPGA, 660K LE, 1.5GHz | Intel
MPN: 10AS066K1F35I1HG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3250 | $3,250.00 |
| 10 | $3087.5 | $30,875.00 |
| 100 | $2762.5 | $276,250.00 |
| 500 | $2437.5 | $1,218,750.00 |
| 1,000 | $2275 | $2,275,000.00 |
Drop-in alternatives for 10AS066K1F35I1HG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AS066K1F35E1HG
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View Datasheet →10AS066H1F34I1HG
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View Datasheet →10AS066K1F35I1HG Maximum Ratings & Electrical Characteristics
| MPN | 10AS066K1F35I1HG |
| Manufacturer | Intel (formerly Altera) |
| Series | Arria 10 SX |
| Logic Elements | 660,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Core Clock | 1.5 GHz |
| Package | 1152-FBGA, FC (35x35 mm) |
| Process Node | TSMC 20 nm |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +100C (Industrial) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
10AS066K1F35I1HG 1152-fbga, fc (35x35 mm) Pin Configuration Guide
Complete pinout information for 10AS066K1F35I1HG (1152-fbga, fc (35x35 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS066K1F35I1HG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS066K1F35I1HG is suitable for 6 applications: 5G Wireless Baseband Prototyping, Radar and Electronic Warfare Signal Processing, Medical Imaging Accelerators (CT/MRI/Ultrasound), Broadcast Video Processing and IPTV, Industrial Machine Vision and Inspection, Software-Defined Radio and SDR Prototyping.
5G Wireless Baseband Prototyping
The 10AS066K1F35I1HG suits 5G baseband prototyping because it pairs a dual ARM Cortex-A9 hard processor system (1.5 GHz) with 660,000 logic elements of programmable fabric. Engineers typically allocate the HPS to L2/L3 protocol stack and OAM management, while FPGA fabric accelerates FFT, channel estimation, LDPC/turbo decoding and beamforming weight computation. The 20 nm Arria 10 process delivers high DSP throughput at lower power than prior Arria generations. Variable-precision DSP blocks run both fixed- and floating-point operators required by 3GPP NR pipelines. The 1152-FBGA F35 package exposes the maximum transceiver count of the die, supporting CPRI or eCPRI fronthaul links to radio units.
Recommended
Radar and Electronic Warfare Signal Processing
For radar and electronic-warfare applications, the 10AS066K1F35I1HG's 660K logic elements and variable-precision DSP blocks deliver the arithmetic density required for pulse compression, MTI filtering, and adaptive beamforming across many channels. The dual Cortex-A9 HPS runs tracker and classification software in parallel with FPGA fabric doing front-end FFT pipelines. The industrial temperature range (-40C to +100C) supports airborne and shipboard deployment. Designers leverage hardened memory controllers to feed wide-bandwidth DDR4 sample buffers. Compared to ASICs, this part allows rapid algorithm iteration while sustaining real-time throughput.
Recommended
Medical Imaging Accelerators (CT/MRI/Ultrasound)
The 10AS066K1F35I1HG fits medical imaging accelerators where real-time reconstruction algorithms (filtered back-projection, iterative reconstruction, beamforming) require both deterministic FPGA pipelines and a control-plane processor for patient I/O. The dual Cortex-A9 subsystem runs the user interface, DICOM stack, and motion-control loops while FPGA fabric handles back-end image reconstruction. The 1152-FBGA F35 package enables the I/O and transceiver bandwidth needed for high-channel-count probe acquisition. Compliance with IEC 60601 patient-safety standards requires careful isolation and firmware validation around this part, but the SoC integration reduces BOM and board area versus a separate MPU plus FPGA architecture.
Recommended
Broadcast Video Processing and IPTV
In broadcast video systems, the 10AS066K1F35I1HG can act as a high-density video processing engine combining HDMI/SDI ingest, multi-stream transcoding glue logic, and audio/video bridging. The 660K LE fabric supports simultaneous 4K/UHD scaling, frame-rate conversion, and HDR tone-mapping pipelines; the dual Cortex-A9 HPS manages control interfaces (CEC, HDCP, IP-based control). The 1152-ball F35 FC-BGA package provides ample I/O for multiple video interfaces. Arria 10 SmartVID feature minimizes dynamic power dissipation for always-on broadcast head-end chassis, where thermal headroom is constrained.
Recommended
Industrial Machine Vision and Inspection
For high-throughput machine vision, the 10AS066K1F35I1HG's fabric delivers parallel image-processing pipelines (Sobel, convolution, optical-flow, deep-learning inference) while the dual Cortex-A9 HPS runs the factory control protocol stack (EtherCAT, PROFINET, Modbus TCP). The industrial temperature range supports factory-floor operation. Hardened PCIe Gen2/Gen3 controllers in the HPS enable direct attachment of GigE Vision or CoaXPress frame grabbers. The 1152-FBGA F35 package supplies sufficient I/O for multi-camera aggregation and trigger distribution.
Recommended
Software-Defined Radio and SDR Prototyping
The 10AS066K1F35I1HG is well suited for software-defined radio prototyping where wide-bandwidth ADC samples feed FPGA fabric running channelizers, demodulators and protocol stacks. The multi-gigabit transceivers exposed by the 1152-ball F35 package support direct ADC/DAC interfaces (JESD204B/C) at rates up to several Gsps. The dual Cortex-A9 HPS hosts a Linux stack running GNU Radio or custom frameworks, while FPGA fabric accelerates physical-layer DSP. Industrial temperature operation and 20 nm low-power process suit both benchtop SDR instruments and deployed tactical radio systems.
Recommended
Recommended Products Summary
Engineering reference data for 10AS066K1F35I1HG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS066K1F35E1HG | 10AS066H1F34I1HG | 10AS066H4F34I3SG | 10AS057K1F35I1HG | 10AS048K1F35I1HG |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-FBGA FC (35x35) | 1152-FBGA FC (35x35) - same | 1152-FBGA FC (35x35) - same | 1152-FBGA FC (35x35) - same | 1152-FBGA FC (35x35) - same | 1152-FBGA FC (35x35) - same |
| Logic Elements | 660,000 | 660,000 | 660,000 | 660,000 | 570,000 | 480,000 |
| HPS Core Clock | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz |
| Temperature Grade | Industrial (-40C to +100C) | Extended | Industrial | Industrial | Industrial | Industrial |
| Speed Grade | K1 | K1 | H1 | H4 | K1 | K1 |
| Process Node | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm |
| Hard Processor System | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 |
| Approximate Unit Price (qty 1) | USD 3,250 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Highest logic-element density in the 10AS066 family (vs 10AS057K1F35I1HG)
- Industrial temperature grade operation (vs 10AS066K1F35E1HG)
- K1 speed grade (highest in family) (vs 10AS066H1F34I1HG)
Design Notes
The 1152-ball flip-chip FBGA package requires matched-length routing, controlled-impedance stack-up, and via-in-pad escape for high-speed transceiver and DDR traces. Use the Intel Arria 10 pin connection guidelines and Quartus pin planner to confirm PCB padstack matches the 1 mm pitch F35 ball map. Estimated: at 1 mm ball pitch, fanout routing typically needs at least 6 PCB layers with HDI micro-vias; budget for at least 8 layers including ground planes adjacent to each signal layer for return-path continuity.
Estimated: a fully utilized 10AS066 die can dissipate 15-25 W in worst-case workloads. With the FC-FBGA F35 package, attach a heatsink or thermal interface material to the package top, and ensure the PCB has continuous copper beneath the device for bottom-side thermal relief. Use Quartus PowerPlay early in the design cycle to model junction temperature; SmartVID dynamically lowers core voltage to manage power dissipation.
Do not assume pin compatibility across different Arria 10 SX package codes (F35 vs F34 vs F29) without consulting the device pin-out file - the F35 and F34 codes signal different ball maps despite shared 1152-ball FC-BGA form factor. Confirm logic-element count and transceiver count before substituting 10AS057 or 10AS048 die variants, as those reduce DSP/LE resources by 14-27% and may break timing closure.
Compliance Information
RoHS compliance and lead-free status confirmed from the Altera/Intel product page. AEC-Q100 not applicable (this is a programmable logic device, not a discrete automotive IC). REACH and halogen-free status not explicitly stated in the verified web data and marked as unknown.
