10AS066K2F35E2LG - 660K LE Arria 10 SX SoC FPGA | Intel / Altera
MPN: 10AS066K2F35E2LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4200 | $4,200.00 |
| 10 | $3990 | $39,900.00 |
| 100 | $3780 | $378,000.00 |
| 500 | $3570 | $1,785,000.00 |
| 1,000 | $3360 | $3,360,000.00 |
Drop-in alternatives for 10AS066K2F35E2LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →10AS066K2F35E2LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 SX |
| Logic Elements | 660,000 |
| Process Technology | 20 nm TSMC |
| Hard Processor System (HPS) | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | 1.5 GHz |
| Adaptive Logic Modules (ALMs) | 248,440 |
| Embedded Memory (M20K + MLAB) | Approx. 87 Mbits |
| DSP Blocks | 396 (variable-precision) |
| Transceivers | 24 channels up to 17.4 Gbps |
| Hard Memory Controllers | DDR3/DDR4 with ECC |
| Package | 1152-ball FCBGA, 35 x 35 mm |
| Core Voltage | 0.9 V |
| Temperature Grade | Industrial (E2 = -40C to +100C junction) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
10AS066K2F35E2LG 1152-ball fcbga, 35 x 35 mm Pin Configuration Guide
Complete pinout information for 10AS066K2F35E2LG (1152-ball fcbga, 35 x 35 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS066K2F35E2LG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS066K2F35E2LG is suitable for 6 applications: Industrial Motor Control and Drives, Software-Defined Radio Baseband, Medical Imaging Pipelines, Broadcast Video Processing, Military and Aerospace Embedded Computing, Test and Measurement Instrumentation.
Industrial Motor Control and Drives
The 10AS066K2F35E2LG is well suited to industrial motor control and servo drives where a single device must execute field-oriented control (FOC) firmware and high-rate current-loop DSP in parallel. Its dual ARM Cortex-A9 HPS runs Linux with EtherCAT or PROFINET stacks and the application code, while 396 variable-precision DSP blocks accelerate Park/Clarke transforms, PID loops, and SVM modulation. With 24 transceivers up to 17.4 Gbps and hard DDR3/DDR4 controllers, the SoC FPGA streams encoder feedback and current samples directly into the FPGA fabric for sub-microsecond loop closure, eliminating the latency of an external DSP. The 1152-ball FCBGA with industrial -40C to +100C junction rating tolerates drive-enclosure thermal stress.
Recommended
Software-Defined Radio Baseband
The 10AS066K2F35E2LG targets software-defined radio baseband where wideband digital down-conversion and channelization must run at line rate. Its 660,000 logic elements plus 396 DSP blocks implement polyphase filter banks, FFTs, and digital up/down converters for LTE, 5G NR, and tactical radio waveforms. The 24 transceivers rated up to 17.4 Gbps interface directly to ADC/DAC front-ends without external SerDes, and the Cortex-A9 HPS handles MAC-layer packet processing and network-stack tasks. Hard DDR3/DDR4 controllers with ECC provide high-bandwidth sample buffering for multi-antenna MIMO architectures, making the 10AS066K2F35E2LG a proven SoC FPGA for SDR platforms.
Recommended
Medical Imaging Pipelines
The 10AS066K2F35E2LG supports medical imaging pipelines including ultrasound beamforming, CT reconstruction, and MRI signal conditioning. Its 660K logic elements plus on-chip M20K memory deliver the parallel fabric needed for delay-and-sum beamforming or back-projection reconstruction. The Cortex-A9 HPS runs the user interface, DICOM stack, and system orchestration, while the FPGA accelerates the pixel-rate processing. The integrated transceiver bank provides LVDS links to high-channel-count ADC arrays, and the hard DDR3/DDR4 controllers with ECC feed the HPS at sustained rates for image buffer management. The industrial temperature range and SoC integration simplify IEC 60601-1 compliant single-board designs.
Recommended
Broadcast Video Processing
The 10AS066K2F35E2LG is a strong fit for broadcast video processing such as 4K/8K up/down/cross conversion, HDR tone-mapping, and SDI/HDMI bridging. Its transceivers natively support 12G-SDI and DisplayPort multi-rate links, eliminating external reclockers. The 660K logic elements plus DSP blocks sustain multi-stream HEVC/H.265 decode or deinterlacing at broadcast pixel rates, and the Cortex-A9 HPS manages network, control, and metadata. Hard memory controllers feed frame buffers at sustained rates required by 4K60 4:4:4 pipelines, making this SoC FPGA a popular choice for production switchers and broadcast encoders.
Recommended
Military and Aerospace Embedded Computing
The 10AS066K2F35E2LG fits military and aerospace embedded computing applications including radar preprocessing, electronic warfare front-ends, and avionics display units. Its 660K logic elements plus hardened ARM Cortex-A9 HPS deliver the determinism and SWaP-C reduction that single-board computers require for airborne platforms. The transceiver bank supports high-speed serial links to RF converters and chassis backplanes, while the industrial temperature grade and ruggedized FCBGA packaging handle vibration and thermal extremes. Partial reconfiguration allows mission-mode swapping of FPGA firmware in flight, a common requirement for adaptive EW systems.
Recommended
Test and Measurement Instrumentation
The 10AS066K2F35E2LG is suitable for test and measurement instrumentation such as high-speed digitizers, arbitrary waveform generators, and protocol analyzers. Its 660K logic elements implement real-time DSP including FIR/IIR filtering, FFT-based spectrum analysis, and trigger logic. The 24 transceivers aggregate multi-channel ADC/DAC data at multi-gigabit rates, and the Cortex-A9 HPS provides a Linux host for the user interface, file storage, and SCPI command parsing over Ethernet or USB. Hard memory controllers with ECC support deep acquisition memory, making the 10AS066K2F35E2LG a common SoC FPGA in mid-range oscilloscopes and protocol testers.
Recommended
Recommended Products Summary
Engineering reference data for 10AS066K2F35E2LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS066K2F35E1HG | 10AS066K1F35E1HG | 10AS066K1F35I1HG | 10AS066H3F34I2SG | 10AS066H2F34I2SG | 10AS066H4F34I3LG |
|---|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 1152-FCBGA, 35x35 mm | 1152-FCBGA, 35x35 mm - same | 1152-FCBGA, 35x35 mm - same | 1152-FCBGA, 35x35 mm - same | 1152-FCBGA, 34x34 mm - same family | 1152-FCBGA, 34x34 mm - same family | 1152-FCBGA, 34x34 mm - same family |
| Logic Elements | 660,000 | 660,000 - same | 660,000 - same | 660,000 - same | 660,000 - same | 660,000 - same | 660,000 - same |
| HPS | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 - same | Dual ARM Cortex-A9 - same | Dual ARM Cortex-A9 - same | Dual ARM Cortex-A9 - same | Dual ARM Cortex-A9 - same | Dual ARM Cortex-A9 - same |
| Transceivers | 24 ch up to 17.4 Gbps (K2) | 24 ch up to 17.4 Gbps (K2) | 12 ch (K1, fewer) | 12 ch (K1, fewer) | 12 ch (H3 speed bin) | 12 ch (H2 speed bin) | 24 ch up to 17.4 Gbps (H4 fastest) |
| Temperature Grade | E2 industrial (-40C to +100C) | E1 industrial | E1 industrial | I industrial | I industrial | I industrial | I industrial |
| Speed Bin | K2 (mid-high) | K2 (mid-high) | K1 (mid) | K1 (mid) | H3 (high) | H2 (lower) | H4 (fastest) |
| Unit Price (qty 1, USD) | 4200.00 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Mid-density SoC FPGA with highest mid-range transceiver count (vs 10AS066K1F35E1HG)
- Wider industrial temperature envelope than E1 grade (vs 10AS066K2F35E1HG)
- Higher performance tier than H3/H2 speed bins (vs 10AS066H3F34I2SG)
Design Notes
Estimated: route the 1152-ball FCBGA on at least a 12-layer PCB using 1oz outer / 0.5oz inner copper, with microvia-in-pad stack-up and 0.4 mm ball pitch escape rules. Allocate dedicated GND planes on layers 2 and 11 for return-path integrity of the multi-gigabit transceivers, and follow the Altera Arria 10 SX symbol/pin-out file exactly when generating the land pattern.
Estimated: at full utilization (660K LEs + 24 transceivers + dual Cortex-A9 HPS active) the device can dissipate 15-25 W. Use a thermal resistance model from the Arria 10 SX thermal user guide; for a junction ceiling of 100C in still air, a heat-spreader with thermal interface material and chassis thermal conduction is required. Do not rely on the FCBGA package alone for sustained full-load operation.
Always source the exact OPN bitstream from Quartus Prime for the specific 10AS066K2F35E2LG variant - the K1/K2 and H2/H3/H4 speed bins are not interchangeable for compiled FPGA images because transceiver channel count and timing closure differ. Verify the Arria 10 SX ordering part number label on the reel against the BOM before board assembly to avoid silent OPN mismatches that cause JTAG-ID errors at bring-up.
Compliance Information
RoHS and REACH compliance per Altera/Intel product page. AEC-Q100 not applicable for FPGAs; industrial temperature grade qualifies most industrial/embedded applications. Halogen-free status not stated in verified web data.
