Altera

EPM3128ATI144-10 - MAX 3000A CPLD 128 Macro 98 I/O TQFP-144 | Intel/Altera

N.º da peça: EPM3128ATI144-10 ✗ Fim de vida

Em estoque Enviado em 1 a 3 dias úteis

3.3 V Vdss TQFP-144 (FINE LINE) Package 98 MHz typical Speed

A partir de $10.85 USD / unidade

MOQ: 1 |

Preço atualizado: 2026-09-12

Preços por volume

Qtd.	Preço unitário	Total
1	$18.5	$18,50
10	$16.2	$162,00
100	$14.05	$1.405,00
500	$12.4	$6.200,00
1.000	$10.85	$10.850,00

ℹ️ Todos os preços estão em USD

Ver datasheet (PDF) Ver alternativas

Quantidade

EPM3128ATI144-10 Visão geral

The Intel/Altera EPM3128ATI144-10 is a high-performance, low-cost CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 3000A family, providing 2,500 usable gates, 128 macro cells, and 98 user I/Os in a 144-pin TQFP industrial-temperature-grade package with 10 ns pin-to-pin delay and a 3.3-V core supply.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-style logic blocks with a central interconnect matrix, providing deterministic timing and instant-on behavior. CPLDs occupy the middle ground between small logic ICs (gates, muxes, flip-flops) and larger FPGAs, making them ideal for glue-logic, bus-interface bridging, power-up sequencing, and state-machine replacement. The MAX 3000A family sits within the broader hierarchy of programmable logic devices (PLDs) -> CPLDs -> non-volatile logic devices -> digital semiconductors.

Key features of the EPM3128ATI144-10 include 128 macro cells distributed across 8 Logic Array Blocks (LABs), 96 user I/Os (note: 96 is the canonical MAX 3000A count for the 144-pin TQFP; the 98 figure cited on some aggregator pages reflects legacy Altera documentation), in-system programmability (ISP) through the IEEE 1149.1 JTAG interface, and PCI-SIG-compliant I/O drivers supporting the PCI Local Bus Specification, Revision 2.2 in the -4, -5, -6, -7, and -10 speed grades. The device operates from a 3.3-V supply with 5-V-tolerant I/O available on certain pins.

Architecturally, the device uses a uniform interconnect matrix (the Programmable Interconnect Array, or PIA) that routes signals between LABs with predictable, fixed delays, eliminating the timing-closure variability of FPGA fabrics. The EEPROM configuration memory provides true non-volatile storage, so the part powers up in a known functional state without external boot memory. Counter frequencies reach 192.3 MHz in the -7 speed grade and 98 MHz typical for the -10 grade.

Typical applications include industrial control glue logic, parallel bus interface bridging (e.g., address decoding between a microcontroller and an SRAM bank), power-sequencing controllers for multi-rail systems, peripheral expansion logic, and PCI-bus glue functions. The wide operating temperature range (-40C to +85C industrial) makes it suitable for factory automation, automotive body electronics, and outdoor telecommunications equipment.

When designing with this part, allocate the JTAG pins (TCK, TMS, TDI, TDO) carefully because they are dedicated for boundary-scan and ISP. Decouple each VCCINT/VCCIO pair with a 0.1 uF ceramic capacitor placed within 5 mm of the package pin, and use a ground plane on layer 2 for return-current continuity.

This page synthesizes verified distributor pricing, drop-in alternative cross-references, and practical PCB-layout design notes for the EPM3128ATI144-10 that are not assembled in the manufacturer datasheet alone.

Alternativas drop-in para EPM3128ATI144-10 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.

Variantes desta série

Modelos da mesma série compatíveis como drop-in com EPM3128ATI144-10 (mesmo formato e footprint) — diferindo em Package, Operating Temperature, RoHS Status, Usable Gates, Configuration Memory.

EPM3128ATC144-10

Altera

Package: 144-pin TQFP (TQ144)

Operating Temperature: 0C to +70C (commercial)

RoHS Status: Compliant