Intel

EPM3256AT1144-10S - MAX 3000A CPLD, 256 Macro, TQFP-144 | Intel

N.º da peça: EPM3256AT1144-10S ✗ Fim de vida

Em estoque Enviado em 1 a 3 dias úteis

3.3 V Vdss TQFP-144 Package

A partir de $21.3 USD / unidade

MOQ: 1 |

Preço atualizado: 2026-09-12

Preços por volume

Qtd.	Preço unitário	Total
1	$38.5	$38,50
10	$34.2	$342,00
100	$28.9	$2.890,00
500	$24.5	$12.250,00
1.000	$21.3	$21.300,00

ℹ️ Todos os preços estão em USD

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EPM3256AT1144-10S Visão geral

The Intel (formerly Altera) EPM3256AT1144-10S is a member of the MAX 3000A family of high-density, in-system programmable CMOS complex programmable logic devices (CPLDs). Housed in a 144-pin Thin Quad Flat Pack (TQFP) and offering 256 macrocells with a 10 ns pin-to-pin logic delay, this device targets glue-logic integration, bus interfacing, and state-machine consolidation in industrial, telecom, and embedded designs. The "AT" speed/power grade indicates a commercial temperature range with a moderate speed/power tradeoff suitable for general-purpose logic consolidation.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple PAL/GAL devices and FPGAs in the programmable logic hierarchy. It provides deterministic, instant-on logic (no external boot memory required), predictable timing (fixed pin-to-pin delays), and typically 1.8V-3.3V core operation with multi-voltage I/O support. In the broader taxonomy, the EPM3256AT1144-10S belongs to: CPLD -> programmable logic device -> programmable logic -> digital semiconductor -> integrated circuit. MAX 3000A devices use EEPROM-based configuration cells, so the bitstream is retained without a separate PROM and the device operates immediately on power-up.

Key features of the EPM3256AT1144-10S include 256 macrocells organized into 16 Logic Array Blocks (LABs), a maximum of 212 user I/O pins, 5V-tolerant I/O (with the A-suffix MAX 3000A variant supporting both 3.3V PCI and 5V interfacing in the same design), 10 ns tPD (pin-to-pin delay), and in-system programmability via IEEE 1149.1 JTAG. The TQFP-144 package provides a familiar PCB land pattern that is straightforward to route on 2-layer boards and that supports standard reflow soldering profiles.

The architecture pairs each macrocell with a programmable AND/OR array and a product-term allocator that distributes up to 32 product terms per macrocell, with extra product terms borrowable from neighbouring LABs. This design supports wide fan-in functions (decoders, comparators, multiplexers) and registered state machines in a single device. The MultiVolt I/O pins interface with 2.5V, 3.3V, and 5.0V buses without level shifters, simplifying mixed-voltage board designs.

Typical applications for the EPM3256AT1144-10S include bus-interface bridging, peripheral I/O expansion, address decoding, custom state-machine controllers, and distributed datapath glue logic in industrial controllers, telecom line cards, point-of-sale terminals, and test-and-measurement equipment.

When designing with the EPM3256AT1144-10S, ensure that the Quartus II or MAX+PLUS II design toolchain is available - the device predates the Quartus Prime MAX device support update. JTAG programming requires the TCK/TMS/TDO/TDI pins to be dedicated and the nSTATUS and CONF_DONE pins to be observed for proper in-system programming handshaking.

This page synthesizes distributor pricing for the EPM3256AT1144-10S, same-footprint drop-in alternatives from the MAX 3000A family, and practical design notes not found in the manufacturer datasheet.

Alternativas drop-in para EPM3256AT1144-10S — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.

Variantes desta série

Modelos da mesma série compatíveis como drop-in com EPM3256AT1144-10S (mesmo formato e footprint) — diferindo em Package, Operating Temperature, Usable Gates, User I/Os, Mounting Type.

EPM3128ATC144-10

Altera

Package: 144-pin TQFP (TQ144)

Operating Temperature: 0C to +70C (commercial)

Usable Gates: 2,500 (typical)