EPM3256AT1144-10S - MAX 3000A CPLD, 256 Macro, TQFP-144 | Intel
MPN: EPM3256AT1144-10S ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.9 | $2,890.00 |
| 500 | $24.5 | $12,250.00 |
| 1,000 | $21.3 | $21,300.00 |
Drop-in alternatives for EPM3256AT1144-10S — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EPM3256AT1144-10S Maximum Ratings & Electrical Characteristics
| Family | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 256 |
| Logic Array Blocks (LABs) | 16 |
| Maximum User I/O Pins | 212 |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Package | TQFP-144 |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +85C (commercial) |
| Supply Voltage - Core | 3.3 V |
| I/O Voltage Support | 2.5V / 3.3V / 5.0V MultiVolt |
| Programmable Interconnect | EEPROM-based, non-volatile |
| In-System Programming | Yes, via IEEE 1149.1 JTAG |
| Configuration Cells | EEPROM (instant-on, no external PROM) |
EPM3256AT1144-10S Pin Configuration
| Pin 1 | I/O — User I/O pin (bank 1) |
| Pin 2 | I/O — User I/O pin (bank 1) |
| Pin 3 | I/O — User I/O pin (bank 1) |
| Pin 4 | I/O — User I/O pin (bank 1) |
| Pin 5 | I/O — User I/O pin (bank 1) |
| Pin 6 | I/O — User I/O pin (bank 1) |
| Pin 7 | I/O — User I/O pin (bank 1) |
| Pin 8 | I/O — User I/O pin (bank 1) |
| Pin 9 | I/O — User I/O pin (bank 1) |
| Pin 10 | I/O — User I/O pin (bank 1) |
| Pin 11 | I/O — User I/O pin (bank 1) |
| Pin 12 | I/O — User I/O pin (bank 1) |
| Pin 13 | I/O — User I/O pin (bank 1) |
| Pin 14 | I/O — User I/O pin (bank 1) |
| Pin 15 | GND — Ground |
| Pin 16 | I/O — User I/O pin (bank 1) |
| Pin 17 | I/O — User I/O pin (bank 1) |
| Pin 18 | I/O — User I/O pin (bank 1) |
| Pin 19 | I/O — User I/O pin (bank 1) |
| Pin 20 | I/O — User I/O pin (bank 1) |
| Pin 21 | I/O — User I/O pin (bank 1) |
| Pin 22 | I/O — User I/O pin (bank 1) |
| Pin 23 | I/O — User I/O pin (bank 1) |
| Pin 24 | I/O — User I/O pin (bank 1) |
| Pin 25 | VCCINT — Core supply voltage (3.3V) |
| Pin 26 | I/O — User I/O pin (bank 2) |
| Pin 27 | I/O — User I/O pin (bank 2) |
| Pin 28 | I/O — User I/O pin (bank 2) |
| Pin 29 | I/O — User I/O pin (bank 2) |
| Pin 30 | I/O — User I/O pin (bank 2) |
| Pin 31 | I/O — User I/O pin (bank 2) |
| Pin 32 | I/O — User I/O pin (bank 2) |
| Pin 33 | I/O — User I/O pin (bank 2) |
| Pin 34 | I/O — User I/O pin (bank 2) |
| Pin 35 | I/O — User I/O pin (bank 2) |
| Pin 36 | GND — Ground |
| Pin 37 | I/O — User I/O pin (bank 2) |
| Pin 38 | I/O — User I/O pin (bank 2) |
| Pin 39 | I/O — User I/O pin (bank 2) |
| Pin 40 | I/O — User I/O pin (bank 2) |
| Pin 41 | I/O — User I/O pin (bank 2) |
| Pin 42 | I/O — User I/O pin (bank 2) |
| Pin 43 | I/O — User I/O pin (bank 2) |
| Pin 44 | I/O — User I/O pin (bank 2) |
| Pin 45 | I/O — User I/O pin (bank 2) |
| Pin 46 | I/O — User I/O pin (bank 2) |
| Pin 47 | I/O — User I/O pin (bank 2) |
| Pin 48 | I/O — User I/O pin (bank 2) |
| Pin 49 | VCCIO — I/O supply voltage (3.3V/2.5V) |
| Pin 50 | I/O — User I/O pin (bank 3) |
| Pin 51 | I/O — User I/O pin (bank 3) |
| Pin 52 | I/O — User I/O pin (bank 3) |
| Pin 53 | I/O — User I/O pin (bank 3) |
| Pin 54 | I/O — User I/O pin (bank 3) |
| Pin 55 | I/O — User I/O pin (bank 3) |
| Pin 56 | I/O — User I/O pin (bank 3) |
| Pin 57 | I/O — User I/O pin (bank 3) |
| Pin 58 | GND — Ground |
| Pin 59 | I/O — User I/O pin (bank 3) |
| Pin 60 | I/O — User I/O pin (bank 3) |
| Pin 61 | I/O — User I/O pin (bank 3) |
| Pin 62 | I/O — User I/O pin (bank 3) |
| Pin 63 | I/O — User I/O pin (bank 3) |
| Pin 64 | I/O — User I/O pin (bank 3) |
| Pin 65 | I/O — User I/O pin (bank 3) |
| Pin 66 | I/O — User I/O pin (bank 3) |
| Pin 67 | I/O — User I/O pin (bank 3) |
| Pin 68 | I/O — User I/O pin (bank 3) |
| Pin 69 | I/O — User I/O pin (bank 3) |
| Pin 70 | VCCINT — Core supply voltage (3.3V) |
| Pin 71 | I/O — User I/O pin (bank 4) |
| Pin 72 | I/O — User I/O pin (bank 4) |
| Pin 73 | I/O — User I/O pin (bank 4) |
| Pin 74 | I/O — User I/O pin (bank 4) |
| Pin 75 | I/O — User I/O pin (bank 4) |
| Pin 76 | I/O — User I/O pin (bank 4) |
| Pin 77 | I/O — User I/O pin (bank 4) |
| Pin 78 | I/O — User I/O pin (bank 4) |
| Pin 79 | GND — Ground |
| Pin 80 | I/O — User I/O pin (bank 4) |
| Pin 81 | I/O — User I/O pin (bank 4) |
| Pin 82 | I/O — User I/O pin (bank 4) |
| Pin 83 | I/O — User I/O pin (bank 4) |
| Pin 84 | I/O — User I/O pin (bank 4) |
| Pin 85 | I/O — User I/O pin (bank 4) |
| Pin 86 | I/O — User I/O pin (bank 4) |
| Pin 87 | I/O — User I/O pin (bank 4) |
| Pin 88 | I/O — User I/O pin (bank 4) |
| Pin 89 | I/O — User I/O pin (bank 4) |
| Pin 90 | VCCIO — I/O supply voltage (3.3V/2.5V) |
| Pin 91 | TDI — JTAG Test Data In |
| Pin 92 | TMS — JTAG Test Mode Select |
| Pin 93 | TCK — JTAG Test Clock |
| Pin 94 | nSTATUS — Programming status output (active-low) |
| Pin 95 | CONF_DONE — Configuration done output |
| Pin 96 | I/O — User I/O pin (bank 4) |
| Pin 97 | I/O — User I/O pin (bank 4) |
| Pin 98 | I/O — User I/O pin (bank 4) |
| Pin 99 | I/O — User I/O pin (bank 4) |
| Pin 100 | I/O — User I/O pin (bank 4) |
| Pin 101 | GND — Ground |
| Pin 102 | I/O — User I/O pin (bank 4) |
| Pin 103 | I/O — User I/O pin (bank 4) |
| Pin 104 | I/O — User I/O pin (bank 4) |
| Pin 105 | I/O — User I/O pin (bank 4) |
| Pin 106 | I/O — User I/O pin (bank 4) |
| Pin 107 | I/O — User I/O pin (bank 4) |
| Pin 108 | I/O — User I/O pin (bank 4) |
| Pin 109 | I/O — User I/O pin (bank 4) |
| Pin 110 | I/O — User I/O pin (bank 4) |
| Pin 111 | I/O — User I/O pin (bank 4) |
| Pin 112 | VCCINT — Core supply voltage (3.3V) |
| Pin 113 | I/O — User I/O pin (bank 3) |
| Pin 114 | I/O — User I/O pin (bank 3) |
| Pin 115 | I/O — User I/O pin (bank 3) |
| Pin 116 | I/O — User I/O pin (bank 3) |
| Pin 117 | I/O — User I/O pin (bank 3) |
| Pin 118 | I/O — User I/O pin (bank 3) |
| Pin 119 | I/O — User I/O pin (bank 3) |
| Pin 120 | GND — Ground |
| Pin 121 | I/O — User I/O pin (bank 3) |
| Pin 122 | I/O — User I/O pin (bank 3) |
| Pin 123 | I/O — User I/O pin (bank 3) |
| Pin 124 | I/O — User I/O pin (bank 3) |
| Pin 125 | I/O — User I/O pin (bank 3) |
| Pin 126 | I/O — User I/O pin (bank 3) |
| Pin 127 | I/O — User I/O pin (bank 3) |
| Pin 128 | I/O — User I/O pin (bank 3) |
| Pin 129 | I/O — User I/O pin (bank 3) |
| Pin 130 | VCCIO — I/O supply voltage (3.3V/2.5V) |
| Pin 131 | I/O — User I/O pin (bank 2) |
| Pin 132 | I/O — User I/O pin (bank 2) |
| Pin 133 | I/O — User I/O pin (bank 2) |
| Pin 134 | I/O — User I/O pin (bank 2) |
| Pin 135 | I/O — User I/O pin (bank 2) |
| Pin 136 | I/O — User I/O pin (bank 2) |
| Pin 137 | I/O — User I/O pin (bank 2) |
| Pin 138 | GND — Ground |
| Pin 139 | I/O — User I/O pin (bank 2) |
| Pin 140 | I/O — User I/O pin (bank 2) |
| Pin 141 | TDO — JTAG Test Data Out |
| Pin 142 | I/O — User I/O pin (bank 1) |
| Pin 143 | I/O — User I/O pin (bank 1) |
| Pin 144 | I/O — User I/O pin (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3256AT1144-10S is suitable for 6 applications: Industrial Controller Glue Logic, Telecom Line-Card Interface Bridging, Point-of-Sale Terminal I/O Expansion, Test & Measurement Front-End Logic, Legacy 5V Peripheral Interfacing, State-Machine Controller.
Industrial Controller Glue Logic
The EPM3256AT1144-10S consolidates address decoding, bus arbitration, and peripheral-chip-enable generation into a single non-volatile device in industrial PLC and motor-controller boards. Its 256 macrocells comfortably absorb dozens of decoded selects, watchdog timers, and PWM synchronizers that would otherwise require multiple 74-series logic gates. The 10 ns tPD is sufficient for 16-bit ISA-style buses at 33 MHz, and the 3.3V core plus 5V-tolerant I/O let it bridge between legacy 5V sensors and modern 3.3V microcontrollers on the same board.
Recommended
Telecom Line-Card Interface Bridging
In telecom line cards the EPM3256AT1144-10S bridges between backplane buses (e.g., H.110 or CompactPCI) and per-channel framer/serializer ASICs, providing bus-width conversion, parity generation, and interrupt steering. Its 212 available user I/Os in the TQFP-144 package handle 32-bit wide datapaths plus side-band control signals. EEPROM-based instant-on configuration eliminates the boot delay of SRAM-based FPGAs, making the device attractive for line cards that must respond to backplane polling within milliseconds of power-up.
Recommended
Point-of-Sale Terminal I/O Expansion
POS terminals integrate keypads, magnetic-stripe readers, thermal printers, displays, and Ethernet controllers - each with different bus widths and timing requirements. The EPM3256AT1144-10S acts as a multi-protocol bus arbiter and I/O expander, replacing 4-6 discrete PAL/GAL devices with a single 256-macrocell CPLD. The instant-on EEPROM configuration avoids the configuration-time delay of an SRAM FPGA at power-up, ensuring the terminal is ready for first-card insertion within milliseconds.
Recommended
Test & Measurement Front-End Logic
Bench-top oscilloscopes, logic analyzers, and data-acquisition front-ends use the EPM3256AT1144-10S to implement trigger-pattern matching, channel-to-channel skew correction, and front-panel knob/switch multiplexing. The deterministic 10 ns pin-to-pin delay simplifies timing-budget calculations across the analog front end. The MultiVolt I/O allows the same CPLD to interface with 5V analog ASICs and 3.3V FPGAs in the same signal chain, removing external level shifters.
Recommended
Legacy 5V Peripheral Interfacing
Modern 1.8V or 3.3V ASICs and microcontrollers often need to drive 5V legacy peripherals (industrial sensors, vacuum-fluorescent displays, older parallel-port chips). The EPM3256AT1144-10S's 5V-tolerant MultiVolt I/O provides a level-shifting bridge without external buffers, while its 3.3V core keeps power dissipation reasonable. This application exploits the unique 5V-tolerant I/O of the MAX 3000A family, a feature not available on most newer CPLD families.
Recommended
State-Machine Controller
The EPM3256AT1144-10S implements complex registered state machines in a single device - up to 16 LABs each containing 16 macrocells can encode deeply nested FSMs that would otherwise require multiple PLDs. Product-term borrowing across LABs allows wide fan-in states (16-20 inputs) for protocol encoders, sequencers, and multi-stage controllers. The non-volatile EEPROM configuration preserves state-machine logic through power cycles without external boot memory.
Recommended
Recommended Products Summary
Engineering reference data for EPM3256AT1144-10S — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3256ATC144-10N | EPM3256ATI144-10N | EPM3128ATC144-10N | EPM3128ATI144-10 |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | TQFP-144 | TQFP-144 (same) | TQFP-144 (same) | TQFP-144 (same) | TQFP-144 (same) |
| Macrocells | 256 | 256 | 256 | 128 (-50%) | 128 (-50%) |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns |
| Operating Temperature | 0C to +85C | 0C to +85C (commercial) | -40C to +85C (industrial) | 0C to +85C (commercial) | -40C to +85C (industrial) |
| Core Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| 5V-Tolerant I/O | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
| Approx Unit Price (qty-1, USD) | $38.50 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Highest user I/O count in the MAX 3000A TQFP-144 family (vs EPM3128ATC144-10N)
- 256 macrocells in a single TQFP-144 device (vs EPM3128ATC144-10N)
- 5V-tolerant MultiVolt I/O with 3.3V core (vs MAX II family (EPM240T100C5N))
Design Notes
The TQFP-144 package has a 0.5 mm pitch with thermal/exposed-pad requirements that demand careful PCB layout. Use at least 4-layer stack-up with a solid ground plane directly beneath the device to provide low-inductance return paths for the 212 high-speed I/O signals. JTAG traces (TDI, TDO, TMS, TCK, nSTATUS, CONF_DONE) should be kept short and length-matched for reliable in-system programming at higher TCK frequencies. Decoupling: place one 100 nF ceramic capacitor per VCCINT and VCCIO pin pair within 2 mm of the package, plus a 10 µF bulk capacitor near the device for low-frequency decoupling.
Although the MAX 3000A is not an SRAM-based FPGA and does not require special boot sequencing, simultaneous-switching output (SSO) noise can still corrupt adjacent analog signals when many I/O pins toggle together. Limit SSO count to 16-20 outputs per bank at full drive strength, or use the Quartus II slow-slew-rate option to reduce di/dt. For 5V-interfacing pins, observe the maximum source-current spec (per-pin and per-bank) from the datasheet; exceeding these limits can cause permanent device damage. Series-termination resistors (22-33 ohm) on clock outputs help control overshoot on long traces.
A common mistake is using Quartus Prime without installing the legacy MAX 3000A device support package - synthesis will fail with "device not supported" errors. Engineers should also note that the EPM3256AT1144-10S uses a non-volatile EEPROM configuration, so any logic change requires a JTAG re-programming cycle (typically 1-3 seconds with ByteBlasterMV or USB-Blaster cables). Mixing industrial-temperature and commercial-temperature MAX 3000A parts on the same JTAG chain is permitted only when the chain software is configured to match the lowest-temperature part in the chain.
Compliance Information
RoHS/REACH compliance status depends on specific date code; request CoC from authorized distributor. MAX 3000A is a commercial/industrial product line not AEC-Q100 qualified for automotive applications.
