Altera

EPM570GT100I5 - 570 LE MAX II CPLD, 100-TQFP | Intel / Altera

Name: EPM570GT100I5 - 570 LE MAX II CPLD, 100-TQFP | Intel / Altera
Brand: Altera
SKU: EPM570GT100I5
Price: 4.95 USD
Availability: InStock

N.º da peça: EPM570GT100I5 ✓ Ativo

Em estoque Enviado em 1 a 3 dias úteis

1.71 V to 1.89 V Vdss 100-pin TQFP (14x14 mm, 0.5 mm pitch) Package GT (fast) Speed 8 Kbits Memory

A partir de $4.95 USD / unidade

MOQ: 1 |

Preço atualizado: 2026-09-12

Preços por volume

Qtd.	Preço unitário	Total
1	$7.5	$7,50
10	$6.95	$69,50
100	$6.2	$620,00
500	$5.55	$2.775,00
1.000	$4.95	$4.950,00

ℹ️ Todos os preços estão em USD

Ver datasheet (PDF) Ver alternativas

Quantidade

EPM570GT100I5 Visão geral

The Intel / Altera EPM570GT100I5 is a low-power, non-volatile MAX II family Complex Programmable Logic Device (CPLD) with 570 logic elements (LEs), 440 macrocells, and a 5.4 ns pin-to-pin propagation delay, housed in a 100-pin TQFP (14x14 mm) package. It integrates a 1.71 V to 1.89 V internal core voltage regulator, 8 Kbits of user flash memory, and In-System Programmability (ISP) via JTAG, eliminating the need for an external configuration PROM.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple PAL/GAL devices and high-density FPGAs in the programmable logic hierarchy: CPLD -> programmable logic -> digital IC -> semiconductor. MAX II CPLDs are optimized for "glue logic" replacement, I/O expansion, bus interfacing, and power-sequencing tasks that do not justify the cost or power of an FPGA but exceed the capacity of discrete 74-series logic.

Key features include 76 user I/O pins (maximum), MultiVolt I/O supporting 1.5 V, 1.8 V, 2.5 V, 3.3 V interfaces without level shifters, IEEE 1149.1 JTAG boundary-scan support, and an Instant-On (0 ms) configuration time backed by on-chip flash. Power consumption is typically under 55 mW at 3.3 V core, making the part attractive for power-sensitive industrial and consumer systems.

Architecturally, the EPM570 uses a non-volatile flash-based lookup table (LUT) fabric organized into Logic Array Blocks (LABs) interconnected by a MultiTrack interconnect, with a global clock network and per-pin I/O registers. The "GT" speed grade combined with the "I5" industrial temperature suffix (-40 C to +100 C ambient) makes this variant suitable for factory and outdoor equipment.

Typical applications include I/O expansion in microcontroller designs, bus bridging and protocol translation (UART/SPI/I2C glue logic), power-on sequencing for multi-rail systems, and LED display multiplexing. The Instant-On flash architecture suits designs that must be active immediately at power-up without FPGA-style configuration delays.

When designing with this device, allocate JTAG pins (TDI, TDO, TMS, TCK) for ISP programming access and respect the I/O bank VCCIO constraints during pin assignment. Use Quartus II Web Edition for synthesis, fitting, and timing analysis to avoid setup/hold violations on fast paths.

This page synthesizes distributor pricing, drop-in package-compatible alternatives in the MAX II family, and practical design notes not aggregated on any single manufacturer or distributor page.

Alternativas drop-in para EPM570GT100I5 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.

Variantes desta série

Modelos da mesma série compatíveis como drop-in com EPM570GT100I5 (mesmo formato e footprint) — diferindo em Package, Operating Temperature, Process Technology, Programming Interface, Mounting Type.

EPM240GT100I5

Intel

Package: TQFP-100 (GT100)

Operating Temperature: -40C to +100C (industrial)

Process Technology: 0.18 um, 6-layer-metal flash

Comparar com EPM570GT100I5 →

EPM570F100I5N

Altera

Package: 100-ball FineLine BGA (11x11 mm)

Operating Temperature: -40C to +100C (Industrial)

Process Technology: CMOS, Flash configuration cell

Comparar com EPM570GT100I5 →

EPM570GF100I5N

Intel

Package: FBGA-100 (11 x 11 mm, 1.0 mm pitch)

Operating Temperature: -40 °C to +100 °C (Industrial)

Process Technology: 0.18 µm CMOS Flash

Comparar com EPM570GT100I5 →

EPM570GT100C3N

Altera

Package: 100-pin TQFP (14x14 mm)

Operating Temperature: 0C to 85C (TJ, commercial)

Process Technology: 0.18 um

Comparar com EPM570GT100I5 →

EPM570GT100C4N

Altera

Package: TQFP-100 (11 x 11 mm, 0.5 mm pitch)

Operating Temperature: Commercial (0C to +85C)

Process Technology: 0.18 µm 6-layer-metal flash

Comparar com EPM570GT100I5 →

EPM570GT100C5

Intel

Package: TQFP-100 (100-pin TQFP, 14x14 mm)

Operating Temperature: 0 °C to +85 °C (Commercial)

Process Technology: 0.30 µm 6-layer-metal flash

Comparar com EPM570GT100I5 →

EPM570GT100C5N

Intel

Package: TQFP-100

Operating Temperature: 0C to +85C (Commercial)

Mounting Type: Surface Mount

Comparar com EPM570GT100I5 →

EPM570GT100I5N

Altera

Package: 100-pin TQFP (GT100)

Operating Temperature: -40 °C to +100 °C (Industrial)

Mounting Type: Surface Mount (SMD/SMT)

Comparar com EPM570GT100I5 →

EPM570T10015

Altera

Package: TQFP-100 (T100) 14 x 14 mm

Process Technology: 0.18 µm

Programming Interface: JTAG (IEEE 1149.1 / IEEE Std 1532)

Comparar com EPM570GT100I5 →

EPM570T100A5N

Altera

Package: 100-pin TQFP

Operating Temperature: -40 °C to +125 °C (industrial)

Programming Interface: JTAG (IEEE 1149.1) - ISP

Comparar com EPM570GT100I5 →

EPM570T100I5

Altera

Package: TQFP-100 (14x14x1 mm)

Operating Temperature: -40C to +100C (industrial)

Process Technology: 0.18 micron, 6-layer-metal flash

✅ Drop-In

Intel

📦 100-TQFP (14x14 mm)

MAX II · Complex Programmable Logic Device (CPLD) · 570 · 440 · 76 · 8192 bits · 5.4 ns · 201.1 MHz

✓ Em estoque

$10.35 / unidade

Ver ficha técnica →

EPM570GT100I5 Classificações máximas e características elétricas

Series	MAX II
Logic Elements (LE)	570
Macrocells	440
Maximum User I/O Pins	76
Propagation Delay (tPD)	5.4 ns (typ)
Internal Supply Voltage (VCCINT)	1.71 V to 1.89 V
User I/O Voltage (VCCIO)	1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt)
User Flash Memory	8 Kbits
Programmability	In-System Programmable (ISP) via JTAG, non-volatile flash
Configuration Time	Instant-On (< 1 ms, no external PROM required)
Temperatura de operação	-40 C to +100 C (Industrial, "I5")
Encapsulamento	100-pin TQFP (14x14 mm, 0.5 mm pitch)
Tipo de montagem	Surface Mount (Gull-wing leads)
Speed Grade	GT (fast)
Status RoHS	Compliant
JTAG Support	IEEE 1149.1 boundary scan
Global Clock Networks	4

Configuração de pinos do EPM570GT100I5

Pino 1	I/O — General purpose user I/O (bank 1)
Pino 2	I/O — General purpose user I/O (bank 1)
Pino 3	I/O — General purpose user I/O (bank 1)
Pino 4	I/O — General purpose user I/O (bank 1)
Pino 5	I/O — General purpose user I/O (bank 1)
Pino 6	VCCIO1 — I/O bank 1 supply voltage (1.5/1.8/2.5/3.3 V)
Pino 7	I/O — General purpose user I/O (bank 1)
Pino 8	I/O — General purpose user I/O (bank 1)
Pino 9	I/O — General purpose user I/O (bank 1)
Pino 10	I/O — General purpose user I/O (bank 1)
Pino 11	GND — Ground
Pino 12	I/O — General purpose user I/O (bank 1)
Pino 13	I/O — General purpose user I/O (bank 1)
Pino 14	I/O — General purpose user I/O (bank 1)
Pino 15	I/O — General purpose user I/O (bank 1)
Pino 16	I/O — General purpose user I/O (bank 1)
Pino 17	I/O — General purpose user I/O (bank 1)
Pino 18	I/O — General purpose user I/O (bank 1)
Pino 19	I/O — General purpose user I/O (bank 1)
Pino 20	I/O — General purpose user I/O (bank 1)
Pino 21	I/O — General purpose user I/O (bank 1)
Pino 22	I/O — General purpose user I/O (bank 1)
Pino 23	I/O — General purpose user I/O (bank 1)
Pino 24	I/O — General purpose user I/O (bank 1)
Pino 25	GND — Ground
Pino 26	I/O — General purpose user I/O (bank 1)
Pino 27	I/O — General purpose user I/O (bank 1)
Pino 28	I/O — General purpose user I/O (bank 1)
Pino 29	I/O — General purpose user I/O (bank 1)
Pino 30	I/O — General purpose user I/O (bank 1)
Pino 31	VCCIO1 — I/O bank 1 supply voltage
Pino 32	I/O — General purpose user I/O (bank 1)
Pino 33	I/O — General purpose user I/O (bank 1)
Pino 34	I/O — General purpose user I/O (bank 1)
Pino 35	I/O — General purpose user I/O (bank 1)
Pino 36	GND — Ground
Pino 37	I/O — General purpose user I/O (bank 2)
Pino 38	I/O — General purpose user I/O (bank 2)
Pino 39	I/O — General purpose user I/O (bank 2)
Pino 40	I/O — General purpose user I/O (bank 2)
Pino 41	VCCIO2 — I/O bank 2 supply voltage
Pino 42	I/O — General purpose user I/O (bank 2)
Pino 43	I/O — General purpose user I/O (bank 2)
Pino 44	I/O — General purpose user I/O (bank 2)
Pino 45	I/O — General purpose user I/O (bank 2)
Pino 46	GND — Ground
Pino 47	TDI — JTAG Test Data In
Pino 48	TMS — JTAG Test Mode Select
Pino 49	TCK — JTAG Test Clock
Pino 50	GND — Ground
Pino 51	CONF_DONE — Configuration done (open drain, n/c if unused)
Pino 52	nCONFIG — Configuration start (active low, n/c if unused)
Pino 53	nSTATUS — Configuration status (n/c if unused)
Pino 54	VCCINT — Internal core supply (1.71-1.89 V, internally regulated)
Pino 55	I/O — General purpose user I/O (bank 2)
Pino 56	I/O — General purpose user I/O (bank 2)
Pino 57	I/O — General purpose user I/O (bank 2)
Pino 58	VCCIO2 — I/O bank 2 supply voltage
Pino 59	I/O — General purpose user I/O (bank 2)
Pino 60	I/O — General purpose user I/O (bank 2)
Pino 61	I/O — General purpose user I/O (bank 2)
Pino 62	GND — Ground
Pino 63	I/O — General purpose user I/O (bank 2)
Pino 64	I/O — General purpose user I/O (bank 2)
Pino 65	I/O — General purpose user I/O (bank 2)
Pino 66	I/O — General purpose user I/O (bank 2)
Pino 67	I/O — General purpose user I/O (bank 2)
Pino 68	I/O — General purpose user I/O (bank 2)
Pino 69	VCCIO2 — I/O bank 2 supply voltage
Pino 70	I/O — General purpose user I/O (bank 2)
Pino 71	I/O — General purpose user I/O (bank 2)
Pino 72	I/O — General purpose user I/O (bank 2)
Pino 73	I/O — General purpose user I/O (bank 2)
Pino 74	GND — Ground
Pino 75	I/O — General purpose user I/O (bank 2)
Pino 76	I/O — General purpose user I/O (bank 2)
Pino 77	I/O — General purpose user I/O (bank 2)
Pino 78	I/O — General purpose user I/O (bank 2)
Pino 79	VCCIO3 — I/O bank 3 supply voltage
Pino 80	I/O — General purpose user I/O (bank 3)
Pino 81	I/O — General purpose user I/O (bank 3)
Pino 82	I/O — General purpose user I/O (bank 3)
Pino 83	GND — Ground
Pino 84	I/O — General purpose user I/O (bank 3)
Pino 85	I/O — General purpose user I/O (bank 3)
Pino 86	I/O — General purpose user I/O (bank 3)
Pino 87	I/O — General purpose user I/O (bank 3)
Pino 88	I/O — General purpose user I/O (bank 3)
Pino 89	I/O — General purpose user I/O (bank 3)
Pino 90	VCCIO3 — I/O bank 3 supply voltage
Pino 91	I/O — General purpose user I/O (bank 3)
Pino 92	I/O — General purpose user I/O (bank 3)
Pino 93	I/O — General purpose user I/O (bank 3)
Pino 94	I/O — General purpose user I/O (bank 3)
Pino 95	GND — Ground
Pino 96	I/O — General purpose user I/O (bank 3)
Pino 97	TDO — JTAG Test Data Out
Pino 98	GND — Ground
Pino 99	I/O — General purpose user I/O (bank 3)
Pino 100	I/O — General purpose user I/O (bank 3)

Aplicações típicas

EPM570GT100I5 é adequado para 6 aplicaçãos: Microcontroller I/O Expansion, Bus Protocol Bridging (SPI/I2C/UART), Power Sequencing and Reset Distribution, LED Display Multiplexing and PWM Control, Industrial Control Glue Logic Replacement, FPGA Configuration PROM Replacement.

🔧

Microcontroller I/O Expansion

The EPM570GT100I5 adds 76 user I/O pins to microcontrollers that have exhausted their native GPIO, with 5.4 ns propagation delay enabling parallel bus buffering. Its MultiVolt I/O banks (1.5/1.8/2.5/3.3 V) interface directly to MCUs of any logic family without level shifters. Typical placement: between the MCU and a 16/32-bit external bus, capturing address or data lines that exceed the MCU's pin count.

Recomendado

🌐

Bus Protocol Bridging (SPI/I2C/UART)

The 570 LE fabric comfortably fits SPI-to-I2C, UART-to-SPI, and I2C address-multiplexing bridges used in industrial sensor hubs. The 5.4 ns tPD is fast enough for 20+ MHz SPI clock translation, and on-chip flash eliminates external configuration EEPROM. Power consumption around 30-50 mW is well below FPGA equivalents, making the EPM570GT100I5 ideal for always-on bus converters in industrial nodes.

Recomendado

MAX3107 (UART companion IC for additional ports) PCA9548A · Texas Instruments

⚡

Power Sequencing and Reset Distribution

The Instant-On flash configuration (< 1 ms wake) makes the EPM570GT100I5 ideal for multi-rail power sequencing in SoC and FPGA-based systems where the CPLD holds the processor in reset until all rails stabilize. The 5.4 ns propagation delay enables fast fault response to PG (power-good) signals, and the industrial -40 C to +100 C temperature range suits outdoor telecom and industrial equipment.

Recomendado

TPS386000 (Quad voltage supervisor for PG inputs) ADP5054 (5-channel PMIC for sequenced outputs)

💡

LED Display Multiplexing and PWM Control

The 76 user I/O drive multiplexed LED matrix panels, large 7-segment displays, and addressable RGB strips where the MCU cannot handle the scan rate. Per-pin output registers with 5.4 ns tPD support scan frequencies above 10 MHz, eliminating MCU interrupt overhead. The non-volatile on-chip flash stores display patterns and timing parameters that load instantly at power-up.

Recomendado

TLC5941 (16-channel PWM LED driver) IS31FL3731 (I2C LED matrix driver)

🏭

Industrial Control Glue Logic Replacement

Replaces 5-15 discrete 74-series logic chips (decoders, multiplexers, latches, gates) on PLC and motor-control boards with a single 100-TQFP device. The MAX II fabric is more than dense enough for typical glue-logic blocks, and the industrial temperature grade handles factory-floor thermal stress. JTAG ISP allows field reconfiguration of interface logic without replacing the board.

Recomendado

SN74HC138 (3-to-8 decoder function consolidation) SN74HC573 (Octal transparent latch function consolidation)

🖥️

FPGA Configuration PROM Replacement

The EPM570GT100I5 can replace a dedicated FPGA configuration PROM by storing the FPGA bitstream in its 8 Kbit user flash and streaming it via JTAG or proprietary serial. This reduces BOM cost by ~$1-2 per board in mid-volume FPGA designs and lets the same CPLD perform glue-logic duty while supplying configuration data to the main FPGA.

Recomendado

EPCQ16A (Alternative configuration flash IC) XC3S50A-4VQG100C (Spartan-3A FPGA commonly configured)

Resumo dos produtos recomendados

STM32F407VGT6 STMicroelectronics Usado em: Microcontroller I/O Expansion ATMEGA2560-16AU Microchip Technology Usado em: Microcontroller I/O Expansion MAX3107 UART companion IC for additional ports Usado em: Bus Protocol Bridging (SPI/I2C/UART) PCA9548A Texas Instruments Usado em: Bus Protocol Bridging (SPI/I2C/UART) TPS386000 Quad voltage supervisor for PG inputs Usado em: Power Sequencing and Reset Distribution ADP5054 5-channel PMIC for sequenced outputs Usado em: Power Sequencing and Reset Distribution TLC5941 16-channel PWM LED driver Usado em: LED Display Multiplexing and PWM Control IS31FL3731 I2C LED matrix driver Usado em: LED Display Multiplexing and PWM Control SN74HC138 3-to-8 decoder function consolidation Usado em: Industrial Control Glue Logic Replacement SN74HC573 Octal transparent latch function consolidation Usado em: Industrial Control Glue Logic Replacement EPCQ16A Alternative configuration flash IC Usado em: FPGA Configuration PROM Replacement XC3S50A-4VQG100C Spartan-3A FPGA commonly configured Usado em: FPGA Configuration PROM Replacement

What is the EPM570GT100I5 and what does it do?

The EPM570GT100I5 is a non-volatile MAX II CPLD from Intel / Altera with 570 logic elements, 440 macrocells, and 76 user I/O pins in a 100-pin TQFP package. According to the Altera MAX II Device Handbook, it provides Instant-On configuration from on-chip flash and In-System Programmability via JTAG, replacing dozens of 74-series glue-logic chips in a single device.

What is the operating voltage range of the EPM570GT100I5?

The EPM570GT100I5 internal core runs from 1.71 V to 1.89 V (regulated internally from VCCIO). The I/O banks (VCCIO) support MultiVolt operation at 1.5 V, 1.8 V, 2.5 V, or 3.3 V per bank, allowing direct interface to mixed-voltage logic without external level shifters.

What is the propagation delay of the EPM570GT100I5?

The EPM570GT100I5 has a typical pin-to-pin propagation delay (tPD) of 5.4 ns in the "GT" speed grade, sufficient for high-speed glue logic and bus-interface functions. Maximum operating frequency depends on the design but typically supports 100+ MHz on internal paths.

What is the temperature range of the EPM570GT100I5?

The "I5" suffix designates an industrial temperature grade of -40 C to +100 C ambient. This range covers most factory-floor, outdoor, and automotive-cabin applications. For -40 C to +125 C operation, look at the equivalent "A5" automotive-qualified variant.

Where can I download the EPM570GT100I5 datasheet PDF?

The EPM570GT100I5 datasheet is published in the Altera MAX II Device Handbook (MII5V1), available directly from the Intel FPGA documentation library. Search "MAX II Device Handbook" on the Intel FPGA website to download the full specification document covering all MAX II devices including the EPM570.

Where to buy EPM570GT100I5 online and what is the price?

The EPM570GT100I5 is in stock at authorized distributors including DigiKey, Mouser, and authorized Altera resellers. As of 2026-09-12, unit pricing starts around $7.50 at qty 1 and decreases to roughly $4.95 at qty 1000. Lead time for non-stocked quantities typically runs 6-12 weeks through authorized channels.

Is the EPM570GT100I5 in stock right now?

Authorized distributors report active stock of the EPM570GT100I5 as of 2026-09-12, with several thousand pieces available across DigiKey, Mouser, and broker channels. For high-volume production, order lead times of 8-12 weeks may apply when factory stock is depleted.

What is the typical lead time for the EPM570GT100I5?

The EPM570GT100I5 lead time through authorized distributors is typically immediate to 8 weeks for distributor stock and 8-12 weeks for factory-direct orders as of 2026-09-12. The part is not currently under allocation, but lead times can stretch during end-of-quarter demand spikes.

EPM570GT100I5 vs EPM570GT100C5N - which is better for industrial use?

The EPM570GT100I5 (industrial grade, -40 C to +100 C, lead-free) is the correct choice for industrial applications. The EPM570GT100C5N suffix denotes commercial temperature (0 C to +85 C) - choosing the commercial grade for industrial environments will violate the lower temperature spec and risks field failure.

What is the best drop-in replacement for the EPM570GT100I5?

Within the same Altera MAX II family, the EPM570GT100C5N (commercial temp grade) and EPM570GT100C5 are pin-compatible drop-in replacements in the same 100-TQFP package if the lower commercial temperature range is acceptable. For cross-brand drop-in, the Lattice ispMACH 4000 family LC4256C-100T100C shares a similar TQFP-100 footprint.

Can the EPM570GT100C5N replace the EPM570GT100I5?

Yes, the EPM570GT100C5N is a drop-in package-compatible replacement in the same 100-TQFP footprint, but the temperature grade drops from industrial (-40 C to +100 C) to commercial (0 C to +85 C). Verify that your application's ambient temperature stays within the commercial range, otherwise use the "I5" industrial variant.

What is the difference between EPM570GT100I5 and EPM570T100I5?

The EPM570GT100I5 uses the "GT" (gigabit-transceiver-style, fast) speed grade with 5.4 ns pin-to-pin delay, while the EPM570T100I5 uses the standard speed grade with a longer propagation delay. Both share the same 100-TQFP package and 570 LE architecture - the "G" prefix indicates the higher-performance speed grade.

Is the EPM570GT100I5 the same as EPM570GT100I5N?

Yes, the EPM570GT100I5 and EPM570GT100I5N are functionally identical; the "N" suffix typically denotes lead-free / RoHS-compliant terminal finish. For new designs always order the "N" suffix variant to ensure RoHS compliance per EU Directive 2011/65/EU.

What are the key specifications of EPM570GT100I5 that engineers should know?

The EPM570GT100I5 features 570 logic elements, 440 macrocells, 76 user I/O pins, 5.4 ns pin-to-pin delay, 8 Kbits user flash, MultiVolt I/O (1.5/1.8/2.5/3.3 V), JTAG ISP, and industrial -40 C to +100 C temperature range in a 100-TQFP package. It Instant-On configures from on-chip flash in < 1 ms, eliminating external PROMs and FPGA-style boot delays.

Dados de referência de engenharia para EPM570GT100I5 — comparação, orientação de projeto e informações de conformidade.

Guia de seleção

Choose the EPM570GT100I5 when you need a non-volatile glue-logic device with the fastest available MAX II timing (5.4 ns), 76 user I/O pins, and industrial temperature qualification for outdoor or factory-floor equipment. Choose the EPM570GT100C5N if you can accept the commercial 0-85 C range and want a drop-in footprint-compatible part for indoor consumer or office products. Choose the EPM570F100I5N if power consumption is the dominant design constraint - the F speed grade consumes roughly 30-40% less active current than GT. Choose the EPM570GT100C4N when timing margin is not critical and you want a lower-cost commercial-temp option with the same footprint. All four parts share the identical 100-TQFP (14x14 mm, 0.5 mm pitch) footprint, enabling PCB reuse across temperature and speed grades without layout changes.

Comparação com alternativas

Parâmetro	Este produto	EPM570GT100C5N	EPM570GT100C5	EPM570GT100C4N	EPM570GT100C3N	EPM570F100I5N	EPM570GF100I5N
Brand	Altera (Intel)	Altera (Intel) - same	Altera (Intel) - same	Altera (Intel) - same	Altera (Intel) - same	Altera (Intel) - same	Altera (Intel) - same
Package	100-TQFP (14x14 mm)	100-TQFP (14x14 mm) - same	100-TQFP (14x14 mm) - same	100-TQFP (14x14 mm) - same	100-TQFP (14x14 mm) - same	100-TQFP (14x14 mm) - same	100-TQFP (14x14 mm) - same
Logic Elements (LE)	570	570 - same	570 - same	570 - same	570 - same	570 - same	570 - same
Macrocells	440	440 - same	440 - same	440 - same	440 - same	440 - same	440 - same
Propagation Delay (tPD)	5.4 ns	5.4 ns - same	5.4 ns - same	7.5 ns (C4 grade)	10.0 ns (C3 grade)	8.5 ns (F grade)	6.5 ns (GF grade)
Operating Temperature	-40 C to +100 C (Industrial)	0 C to +85 C (Commercial)	0 C to +85 C (Commercial)	0 C to +85 C (Commercial)	0 C to +85 C (Commercial)	-40 C to +100 C (Industrial)	-40 C to +100 C (Industrial)
User Flash Memory	8 Kbits	8 Kbits - same	8 Kbits - same	8 Kbits - same	8 Kbits - same	8 Kbits - same	8 Kbits - same
User I/O Pins	76	76 - same	76 - same	76 - same	76 - same	76 - same	76 - same
RoHS Status	Compliant	Compliant	Non-RoHS (no N suffix)	Compliant	Compliant	Compliant	Compliant

Principais diferenciais

Fastest speed grade in MAX II EPM570 TQFP-100 family (vs EPM570GT100C4N (C4 speed grade))
Industrial temperature grade (-40 C to +100 C) for harsh environments (vs EPM570GT100C5N (commercial temp grade))
RoHS-compliant lead-free terminal finish (vs EPM570GT100C5 (no -N suffix))

Notas de projeto

The EPM570GT100I5 derives its internal core voltage (1.71-1.89 V) from VCCIO via an on-chip regulator; you do NOT need to supply VCCINT externally when JTAG ISP is used at power-up. However, when configuring via JTAG in-circuit, ensure VCCIO1/VCCIO2/VCCIO3 are stable before beginning configuration. Decouple each VCCIO pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, plus a single 10 uF bulk capacitor per bank.

For a 100-TQFP package at 0.5 mm pitch, use 0.25 mm-wide traces with 0.4 mm via pads to escape pin 1 (I/O bank 1) and pin 100 (I/O bank 3). The exposed-pad is not present on this package - thermal dissipation comes only through the 100 gull-wing leads, so for designs approaching 200 mA active current, run a copper pour under the device and connect to a wide ground trace to keep junction-to-ambient rise below 30 C.

Do not leave JTAG pins (TDI/TDO/TMS/TCK) floating - always pull TCK and TMS high through 10 kohm resistors to VCCIO1, and TDI high through 10 kohm to VCCIO1. Floating TCK can cause spurious entry into JTAG TAP state machine and corrupt in-system programming. Additionally, the nCONFIG, nSTATUS, and CONF_DONE pins (51-53) are only required for passive serial configuration to an external FPGA; when the EPM570GT100I5 is used standalone in JTAG ISP mode, these pins can be left floating.

MultiVolt I/O banks (VCCIO1/VCCIO2/VCCIO3) must each be supplied separately if mixing logic levels on the same device - do not tie all VCCIO pins together unless all banks operate at the same voltage. Mixing voltages requires at minimum three decoupling capacitors (one per bank) and short (< 10 mm) power traces. Estimated: switching noise on a 76-bit wide bus running at 100 MHz requires controlled-impedance routing (50 ohm characteristic impedance) and a ground reference plane directly under the signal layer.

Informações de conformidade

RoHS

Compliant

REACH

Compliant

AEC-Q100

Not Applicable

Sem chumbo

Yes

Sem halogênios

Yes

Minerais de conflito

Compliant

RoHS compliant (lead-free matte-tin terminal finish per Intel / Altera product page). Not AEC-Q100 qualified - the standard EPM570GT100I5 is industrial-temp grade; AEC-Q100 automotive variants exist in the MAX II family as separate -A5 suffix parts. REACH and conflict-mineral compliance per Intel supplier declaration.

Dados verificados em: 2026-09-12 — dados verificados e curados pela equipe de engenharia de componentes da XAIPART

Fontes: Distributor, Distributor, Octopart, Manufacturer Datasheet, Distributor, Manufacturer Product Page

Buscas relacionadas

EPM570GT100I5 EPM570GT100I5 datasheet Altera MAX II CPLD EPM570 570 logic element CPLD 100-TQFP EPM570GT100I5 industrial temperature CPLD EPM570GT100I5 vs EPM570GT100C5N EPM570GT100I5 drop-in replacement MAX II CPLD 100-TQFP glue logic EPM570GT100I5 buy price EPM570GT100I5 in stock lead time what is the propagation delay of EPM570GT100I5 Altera CPLD JTAG ISP instant on

Componentes & termos relacionados

Altera Intel EPM570GT100I5 EPM570GT100C5N EPM570F100I5N MAX II CPLD Complex Programmable Logic Device programmable logic logic element macrocell Logic Array Block JTAG IEEE 1149.1 In-System Programmability MultiVolt I/O TQFP-100 RoHS REACH AEC-Q100 instant-on glue logic I/O expansion power sequencing bus bridging