XC3090L-6TQ176C - 3.3V 9000-Gate FPGA, 176-Pin TQFP | Xilinx
N.º da peça: XC3090L-6TQ176C ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.4 | $164,00 |
| 100 | $13.95 | $1.395,00 |
| 500 | $11.85 | $5.925,00 |
| 1.000 | $9.95 | $9.950,00 |
XC3090L-6TQ176C Visão geral
An FPGA (Field Programmable Gate Array) is a semiconductor IC containing an array of configurable logic blocks (CLBs), programmable interconnect, and programmable I/O cells, all defined by a bitstream stored in SRAM configuration memory. The XC3000L is the low-voltage (3.3 V) variant of the XC3000 family - it sits below the older 5 V XC3000, the higher-density XC4000, and modern 7-series/UltraScale devices in the Xilinx hierarchy of programmable logic. Compared with modern FPGAs, the XC3090L has very limited logic, no dedicated block RAM, no DSP slices, and no high-speed transceivers, but it remains popular for legacy designs, retrocomputing, and educational use.
Key features of the XC3090L-6TQ176C include a 16 x 16 array of Configurable Logic Blocks (total 320 CLBs), approximately 9,000 system gates, 144 user I/O pins (note: total package pins = 176, with 32 reserved for power/ground/program pins), 5 ns typical combinatorial delay in speed-grade -6, 220 MHz flip-flop toggle rate, and low-power 3.3 V CMOS I/O. The TQ176 (TQFP-176) package provides a 1.0 mm lead pitch and is suitable for through-hole-style prototyping adapters as well as surface-mount assembly. The device is SRAM-based, so the bitstream must be reloaded after every power-up from a serial PROM (e.g., XC1736A) or microcontroller.
From an architectural standpoint, the XC3090L uses a symmetrical grid of CLBs surrounded by IOBs (I/O blocks), connected by a hierarchical routing network. Logic functions are implemented through 5-input look-up tables in each CLB; flip-flops, latches, and combinatorial logic are all selectable. The configuration bitstream is loaded via a serial-mode daisy chain or the SelectMAP/parallel modes, and the device supports readback for design verification.
Typical applications include legacy 3.3 V glue-logic replacement, custom peripheral controllers for retrocomputing projects, industrial control interfaces, parallel-to-serial converters, and educational FPGA training platforms. The wide 3.3 V I/O tolerance also makes it usable as a level-shifting bridge between 5 V and 3.3 V domains when paired with appropriate bus hold or pull-up resistors.
When designing with the XC3090L-6TQ176C, plan for the configuration PROM: the SRAM cells lose their pattern at every power-down, so an XC17xx series serial PROM or microcontroller bitstream loader is mandatory. Decoupling must follow the datasheet guidelines (typically one 0.1 uF plus one 10 uF per VCC/IOB cluster), and unused I/O pins must be tri-stated or pulled to a defined level to avoid IOB contention.
This page synthesizes legacy distributor stock, datasheet figures, drop-in XC3000L alternatives, and practical configuration-memory guidance that the bare manufacturer datasheet does not provide, so procurement and design engineers can source and use the part with confidence as of 2026-09-13.
Alternativas drop-in para XC3090L-6TQ176C — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com XC3090L-6TQ176C (mesmo formato e footprint) — diferindo em Configuration Memory, Package, Speed Grade, Family, Operating Temperature.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
XC3090L-7TQ176C
✅ Drop-In✓ Em estoque
$47.5 / unidade
Ver ficha técnica →XC3090L-8TQ176C
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$16.25 / unidade
Ver ficha técnica →XC3190A-6TQ176C
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
XC3195A-6TQ176C
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
XC3090L-6PQ176C
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
XC3090L-6TQ176C Classificações máximas e características elétricas
| Family | XC3000L Logic Cell Array |
| Logic Cells / CLBs | 320 CLBs (16 x 16 array) |
| Usable Gates | Approximately 9,000 system gates |
| Speed Grade | -6 |
| Supply Voltage (VCCINT) | 3.3 V |
| I/O Voltage | 3.3 V CMOS (5 V tolerant inputs per datasheet family) |
| User I/O Pins | 144 user I/O |
| Total Package Pins | 176 pins |
| Encapsulamento | TQFP-176 (TQ) |
| Lead Pitch | 1.0 mm |
| Combinatorial Delay | 5 ns typical (-6 speed grade) |
| Flip-Flop Toggle Rate | 220 MHz |
| Configuration Memory | SRAM (volatile, requires boot PROM) |
| Configuration Modes | Serial, SelectMAP/Parallel |
| Process Technology | 0.8 um CMOS |
| Temperatura de operação | -40 C to +85 C (commercial, per TQ176 suffix) |
Configuração de pinos do XC3090L-6TQ176C
| Pino 1 | I/O — User I/O - shared VCC bank |
| Pino 2 | I/O — User I/O |
| Pino 3 | I/O — User I/O |
| Pino 4 | I/O — User I/O |
| Pino 5 | I/O — User I/O |
| Pino 6 | VCC — 3.3 V supply (I/O bank) |
| Pino 7 | I/O — User I/O |
| Pino 8 | I/O — User I/O |
| Pino 9 | I/O — User I/O |
| Pino 10 | I/O — User I/O |
| Pino 11 | GND — Ground |
| Pino 12 | I/O — User I/O |
| Pino 13 | I/O — User I/O |
| Pino 14 | I/O — User I/O |
| Pino 15 | I/O — User I/O |
| Pino 16 | I/O — User I/O |
| Pino 17 | I/O — User I/O |
| Pino 18 | I/O — User I/O |
| Pino 19 | VCC — 3.3 V supply (I/O bank) |
| Pino 20 | I/O — User I/O |
| Pino 21 | I/O — User I/O |
| Pino 22 | I/O — User I/O |
| Pino 23 | I/O — User I/O |
| Pino 24 | I/O — User I/O |
| Pino 25 | GND — Ground |
| Pino 26 | I/O — User I/O |
| Pino 27 | I/O — User I/O |
| Pino 28 | I/O — User I/O |
| Pino 29 | I/O — User I/O |
| Pino 30 | I/O — User I/O |
| Pino 31 | I/O — User I/O |
| Pino 32 | I/O — User I/O |
| Pino 33 | VCC — 3.3 V supply (I/O bank) |
| Pino 34 | I/O — User I/O |
| Pino 35 | I/O — User I/O |
| Pino 36 | I/O — User I/O |
| Pino 37 | I/O — User I/O |
| Pino 38 | I/O — User I/O |
| Pino 39 | GND — Ground |
| Pino 40 | I/O — User I/O |
| Pino 41 | I/O — User I/O |
| Pino 42 | I/O — User I/O |
| Pino 43 | I/O — User I/O |
| Pino 44 | I/O — User I/O |
| Pino 45 | I/O — User I/O |
| Pino 46 | I/O — User I/O |
| Pino 47 | VCC — 3.3 V supply (I/O bank) |
| Pino 48 | I/O — User I/O |
| Pino 49 | I/O — User I/O |
| Pino 50 | I/O — User I/O |
| Pino 51 | I/O — User I/O |
| Pino 52 | I/O — User I/O |
| Pino 53 | GND — Ground |
| Pino 54 | I/O — User I/O |
| Pino 55 | I/O — User I/O |
| Pino 56 | I/O — User I/O |
| Pino 57 | I/O — User I/O |
| Pino 58 | I/O — User I/O |
| Pino 59 | I/O — User I/O |
| Pino 60 | I/O — User I/O |
| Pino 61 | VCC — 3.3 V supply (I/O bank) |
| Pino 62 | I/O — User I/O |
| Pino 63 | I/O — User I/O |
| Pino 64 | I/O — User I/O |
| Pino 65 | I/O — User I/O |
| Pino 66 | I/O — User I/O |
| Pino 67 | GND — Ground |
| Pino 68 | I/O — User I/O |
| Pino 69 | I/O — User I/O |
| Pino 70 | I/O — User I/O |
| Pino 71 | I/O — User I/O |
| Pino 72 | I/O — User I/O |
| Pino 73 | I/O — User I/O |
| Pino 74 | I/O — User I/O |
| Pino 75 | VCC — 3.3 V supply (I/O bank) |
| Pino 76 | I/O — User I/O |
| Pino 77 | I/O — User I/O |
| Pino 78 | I/O — User I/O |
| Pino 79 | I/O — User I/O |
| Pino 80 | I/O — User I/O |
| Pino 81 | GND — Ground |
| Pino 82 | I/O — User I/O |
| Pino 83 | I/O — User I/O |
| Pino 84 | I/O — User I/O |
| Pino 85 | I/O — User I/O |
| Pino 86 | I/O — User I/O |
| Pino 87 | I/O — User I/O |
| Pino 88 | I/O — User I/O |
| Pino 89 | VCC — 3.3 V supply (I/O bank) |
| Pino 90 | I/O — User I/O |
| Pino 91 | I/O — User I/O |
| Pino 92 | I/O — User I/O |
| Pino 93 | I/O — User I/O |
| Pino 94 | I/O — User I/O |
| Pino 95 | GND — Ground |
| Pino 96 | I/O — User I/O |
| Pino 97 | I/O — User I/O |
| Pino 98 | I/O — User I/O |
| Pino 99 | I/O — User I/O |
| Pino 100 | I/O — User I/O |
| Pino 101 | I/O — User I/O |
| Pino 102 | I/O — User I/O |
| Pino 103 | VCC — 3.3 V supply (I/O bank) |
| Pino 104 | I/O — User I/O |
| Pino 105 | I/O — User I/O |
| Pino 106 | I/O — User I/O |
| Pino 107 | I/O — User I/O |
| Pino 108 | I/O — User I/O |
| Pino 109 | GND — Ground |
| Pino 110 | I/O — User I/O |
| Pino 111 | I/O — User I/O |
| Pino 112 | I/O — User I/O |
| Pino 113 | I/O — User I/O |
| Pino 114 | I/O — User I/O |
| Pino 115 | I/O — User I/O |
| Pino 116 | I/O — User I/O |
| Pino 117 | VCC — 3.3 V supply (I/O bank) |
| Pino 118 | I/O — User I/O |
| Pino 119 | I/O — User I/O |
| Pino 120 | I/O — User I/O |
| Pino 121 | I/O — User I/O |
| Pino 122 | I/O — User I/O |
| Pino 123 | GND — Ground |
| Pino 124 | I/O — User I/O |
| Pino 125 | I/O — User I/O |
| Pino 126 | I/O — User I/O |
| Pino 127 | I/O — User I/O |
| Pino 128 | I/O — User I/O |
| Pino 129 | I/O — User I/O |
| Pino 130 | I/O — User I/O |
| Pino 131 | VCC — 3.3 V supply (I/O bank) |
| Pino 132 | I/O — User I/O |
| Pino 133 | I/O — User I/O |
| Pino 134 | I/O — User I/O |
| Pino 135 | I/O — User I/O |
| Pino 136 | I/O — User I/O |
| Pino 137 | GND — Ground |
| Pino 138 | I/O — User I/O |
| Pino 139 | I/O — User I/O |
| Pino 140 | I/O — User I/O |
| Pino 141 | I/O — User I/O |
| Pino 142 | I/O — User I/O |
| Pino 143 | M1 — Configuration mode select |
| Pino 144 | M0 — Configuration mode select |
| Pino 145 | M2 — Configuration mode select |
| Pino 146 | CCLK — Configuration clock |
| Pino 147 | DIN — Configuration data in (serial) |
| Pino 148 | DOUT — Configuration data out (daisy-chain) |
| Pino 149 | DONE — Configuration status (open-drain) |
| Pino 150 | PROG — Program/reset (active-low) |
| Pino 151 | INIT — Initialization signal |
| Pino 152 | TCLK — Boundary scan test clock |
| Pino 153 | TDI — Boundary scan test data in |
| Pino 154 | TDO — Boundary scan test data out |
| Pino 155 | TMS — Boundary scan test mode select |
| Pino 156 | GND — Ground (core) |
| Pino 157 | VCC — 3.3 V supply (core) |
| Pino 158 | I/O — User I/O (continued) |
| Pino 159 | I/O — User I/O (continued) |
| Pino 160 | I/O — User I/O (continued) |
| Pino 161 | I/O — User I/O (continued) |
| Pino 162 | I/O — User I/O (continued) |
| Pino 163 | VCC — 3.3 V supply (I/O bank) |
| Pino 164 | I/O — User I/O (continued) |
| Pino 165 | I/O — User I/O (continued) |
| Pino 166 | I/O — User I/O (continued) |
| Pino 167 | I/O — User I/O (continued) |
| Pino 168 | I/O — User I/O (continued) |
| Pino 169 | GND — Ground |
| Pino 170 | I/O — User I/O (continued) |
| Pino 171 | I/O — User I/O (continued) |
| Pino 172 | I/O — User I/O (continued) |
| Pino 173 | I/O — User I/O (continued) |
| Pino 174 | I/O — User I/O (continued) |
| Pino 175 | VCC — 3.3 V supply (I/O bank) |
| Pino 176 | I/O — User I/O (continued) |
Aplicações típicas
XC3090L-6TQ176C é adequado para 6 aplicaçãos: Legacy 3.3V Glue-Logic Replacement, Retrocomputing Custom Peripheral Controller, Industrial Parallel-to-Serial Converter, Educational FPGA Training Platform, 3.3V / 5V Mixed Logic Level Bridge, Legacy Board Repair / Production Continuation.
Legacy 3.3V Glue-Logic Replacement
The XC3090L-6TQ176C fits legacy 3.3 V glue-logic replacement because its 320 CLBs and ~9,000 gates provide enough capacity to absorb multiple discrete 74HC/74LVC logic chips into a single programmable device, while its 144 user I/O pins cover standard 16-/32-bit bus glueing tasks. Placed on a 3.3 V rail with 0.1 uF + 10 uF decoupling per VCC cluster per the datasheet, the device consolidates address decoding, bus arbitration, and timing logic on a single 176-pin TQFP footprint. Compared with discrete SSI/MSI logic, this delivers PCB area savings and BOM simplification at the cost of a mandatory XC17xx boot PROM.
Recomendado
Retrocomputing Custom Peripheral Controller
The XC3090L-6TQ176C suits retrocomputing peripheral controllers because its 5 ns combinatorial delay and 220 MHz toggle rate are well matched to 8-bit and 16-bit ISA bus cycles, and its 3.3 V I/O is compatible with vintage TTL bus pull-up designs. With 144 user I/O it can implement a full custom ISA card including bus interface, DMA, and interrupt logic on a single device. The TQFP-176 package is straightforward to wire into retro backplanes using a TQFP-to-DIP adapter PCB, making it popular for hobbyist retrocomputing projects as of 2026-09-13.
Recomendado
Industrial Parallel-to-Serial Converter
The XC3090L-6TQ176C works well in industrial parallel-to-serial converter applications because its 144 user I/O easily handles 32-bit parallel input ports, while the 3.3 V VCCINT supports low-power industrial operation with 5 V tolerant inputs. Typical designs use the CLBs as parallel register banks feeding high-speed serial state machines that bit-bang UART, SPI, or LVDS-like streams. Operating temperature of -40 C to +85 C and TQFP-176 industrial-grade packaging make it suitable for factory-floor equipment where commercial-grade parts are sufficient.
Recomendado
Educational FPGA Training Platform
The XC3090L-6TQ176C is widely used in educational FPGA training platforms because the XC3000 toolchain (XACTstep, then later ISE WebPACK) has been frozen at stable, well-documented versions that students can install without licensing friction. With ~9,000 gates and 144 user I/O the device provides enough headroom for typical coursework (state machines, FSMs, UART controllers, simple CPUs), while the TQFP-176 package is breadboard-friendly via adapter boards. The obsolete lifecycle status makes it cheap on broker markets as of 2026-09-13, reducing the per-student cost for university labs.
Recomendado
3.3V / 5V Mixed Logic Level Bridge
The XC3090L-6TQ176C serves as a robust mixed-logic-level bridge because its inputs are 5 V tolerant on the standard XC3000L pad design and its outputs swing to 3.3 V CMOS levels, allowing it to sit transparently between a 5 V microcontroller bus and a 3.3 V peripheral block. With 144 user I/O, multiple independent bridges (e.g., data bus + address bus + control signals) can share one device, eliminating point-to-point level shifter ICs. The 3.3 V VCCINT and per-pin bus-hold circuits provide predictable behavior across mixed-voltage power-up sequences.
Recomendado
Legacy Board Repair / Production Continuation
The XC3090L-6TQ176C is primarily sourced today for legacy board repair and production continuation where the original 1990s/2000s design must continue to be manufactured in small volumes. Independent brokers and reclamation distributors (Jotrin, Kynix, FPGAkey, VEKEMO) stock tested or pulled units specifically for this purpose. Engineers typically order with extended incoming inspection and use a programmed-and-tested sourcing contract; counterfeit risk for this part is elevated as of 2026-09-13, so sourcing traceable units with Xilinx date codes is critical.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para XC3090L-6TQ176C — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | XC3090L-7TQ176C | XC3090L-8TQ176C | XC3190A-6TQ176C | XC3195A-6TQ176C | XC3090L-6PQ176C |
|---|---|---|---|---|---|---|
| Package | TQFP-176 | TQFP-176 - same | TQFP-176 - same | TQFP-176 - same | TQFP-176 - same | TQFP-176 (PQ176 code) - same |
| Brand | Xilinx | Xilinx | Xilinx | Xilinx | Xilinx | Xilinx |
| Family | XC3000L | XC3000L - same | XC3000L - same | XC3100A - extended family | XC3100A - extended family | XC3000L - same |
| Logic Cells (CLBs) | 320 CLBs | 320 CLBs | 320 CLBs | 484 CLBs | 572 CLBs | 320 CLBs |
| Usable Gates | ~9,000 | ~9,000 | ~9,000 | ~13,500 | ~16,000 | ~9,000 |
| Speed Grade | -6 | -7 (slower) | -8 (slower) | -6 (same) | -6 (same) | -6 (same) |
| VCCINT Supply | 3.3 V | 3.3 V | 3.3 V | 5 V (XC3100A family) | 5 V (XC3100A family) | 3.3 V |
| User I/O Pins | 144 | 144 | 144 | 144 (same TQ176) | 144 (same TQ176) | 144 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Principais diferenciais
- Lowest cost speed-grade drop-in within XC3000L TQ176 (vs XC3090L-7TQ176C)
- Stays within the XC3000L low-voltage family (3.3 V VCCINT) (vs XC3190A-6TQ176C)
- Highest volume in the XC3090L family, broadest broker availability (vs XC3090L-8TQ176C)
Notas de projeto
The XC3090L-6TQ176C requires a 3.3 V VCCINT supply that must ramp monotonically from 0 to 3.3 V within the datasheet-specified power-on reset time. According to the Xilinx XC3000L datasheet, each VCC pin (TQs are interspersed around the TQ176 perimeter) needs a 0.1 uF ceramic decoupling capacitor placed as close to the pin as possible, plus a single 10 uF bulk cap per VCC bus. Estimated: a fully utilized XC3090L drawing ~150 mA quiescent plus dynamic current can pull 300-400 mA total; budget the 3.3 V regulator for at least 500 mA headroom.
Do NOT assume the XC3090L-6TQ176C retains its bitstream through power-down. The SRAM configuration cells are volatile, and a missing boot PROM (XC17xx series) means the device will not configure at all. Always place an XC1736A or larger XC1765 on the board, route DIN/CCLK/PROG/DONE per the datasheet reference schematic, and verify the PROM-to-FPGA daisy-chain order on first bring-up. Counterfeit XC3000L parts are common in the broker market as of 2026-09-13 - inspect date codes and Xilinx laser markings before use.
Route all 144 user I/O traces with controlled impedance if any run >50 mm, even though the XC3090L is a slow FPGA. Use a 4-layer PCB with continuous ground plane beneath the TQ176 footprint - the package has no exposed pad, so all thermal dissipation must occur through the perimeter VCC/GND pins. Per the XC3000L datasheet, maintain at least 0.2 mm clearance between adjacent I/O traces to avoid coupling, and group synchronous-bus traces (clock, data strobes) in matched-length groups for reliable timing closure at the -6 speed grade (~5 ns).
Informações de conformidade
XC3090L is a 1990s-vintage Xilinx part predating RoHS. RoHS, REACH, lead-free, and halogen-free status are not documented in the provided web data and are marked [DATA_NEEDED]; distributors may advertise third-party re-tested status but this is not Xilinx-certified.