Intel

EPM7128SQC160-15 - MAX 7000 CPLD, 128 Macrocells, 100 I/O | Intel

Артикул: EPM7128SQC160-15 ✗ Снят с производства

В наличии Отправка в течение 1–3 рабочих дней

4.75 V to 5.25 V Vdss 160-BQFP (160-PQFP, 28x28 mm) Package 125 MHz (internal feedback) Speed EEPROM (non-volatile, ~100 erase/program cycles) Memory

От $9.95 USD / шт.

MOQ: 1 |

Цена обновлена: 2026-09-12

Оптовые цены

Кол-во	Цена за ед.	Итого
1	$18.5	$18,50
10	$16.2	$162,00
100	$13.85	$1.385,00
500	$11.4	$5.700,00
1.000	$9.95	$9.950,00

ℹ️ Все цены указаны в USD

Открыть datasheet (PDF) Смотреть аналоги

Количество

EPM7128SQC160-15 Обзор

The Intel (formerly Altera) EPM7128SQC160-15 is a high-density, high-performance EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 7000 family, offering 128 macrocells, 2,500 usable gates, and 100 user I/Os in a 160-pin PQFP package with a 15 ns pin-to-pin propagation delay. Built on Altera's second-generation MAX architecture, it combines non-volatile EEPROM configuration memory with a 5V-tolerant I/O ring, making it suitable for legacy 5V system designs and 3.3V-tolerant interfaces.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits in the digital logic hierarchy between simple PLDs (PALs/GALs) and FPGAs. CPLDs use a deterministic, AND-OR fabric with macrocell-based logic blocks and a global interconnect that guarantees predictable, fixed propagation delays independent of routing density. This deterministic timing makes CPLDs ideal for glue logic, bus decoding, address mapping, state-machine control, and high-speed control-plane tasks where every nanosecond of delay must be accounted for at synthesis time.

Key differentiating features include a maximum operating frequency of 125 MHz (with internal feedback), 4.5 ns logic-element propagation delay, in-system programmability via IEEE 1149.1 JTAG, and support for 5V/3.3V multi-voltage I/O via the MAX 7000S I/O ring. The 160-pin PQFP (Plastic Quad Flat Pack) package provides a generous thermal envelope for industrial and commercial temperature grades. Power consumption is dominated by static I/O current and scales with toggle frequency, with a typical ICC of approximately 100-150 mA at full operation.

Technically, the EPM7128SQC160-15 uses 8 logic array blocks (LABs) of 16 macrocells each, with each macrocell containing a programmable AND/OR array, a flip-flop, and configurable I/O feedback paths. The EEPROM configuration cell retains logic design without external memory, supports 100 erase/program cycles, and allows instant-on behavior at power-up. The JTAG interface supports both boundary-scan testing and in-system programming, enabling board-level test access and field upgrades.

Typical applications include bus-interface glue logic for 5V and 3.3V microcontroller systems, address decoding and chip-select generation for memory and peripheral buses, peripheral control and state-machine implementation in industrial controllers, legacy system replacements for discrete 74-series logic, and high-speed control logic in test-and-measurement equipment. The deterministic timing model also makes the EPM7128SQC160-15 well-suited for protocol bridging between microcontrollers and older peripheral ASICs.

When designing with the EPM7128SQC160-15, note that the part is now in obsolescence transition - many MAX 7000 devices are listed as obsolete at Intel/Altera. Engineers should verify last-time-buy status with the manufacturer and plan migration paths to MAX II or MAX V CPLDs (which are 3.3V/2.5V/1.8V-only and require re-synthesis). Existing designs with stable long-term supply should consider a second-source strategy, since EPM7128SQC160-15 was originally a single-source part.

This page synthesizes distributor pricing, verified drop-in alternatives drawn from the MAX 7000 family, and practical design notes - information not consolidated in the original Altera datasheet. All specifications are cross-checked against the manufacturer datasheet and current distributor listings.

Аналоги без доработки для EPM7128SQC160-15 — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.

Варианты в этой серии

Модели той же серии, совместимые без доработки с EPM7128SQC160-15 (тот же форм-фактор и посадочное место) — отличается по Package, Operating Temperature, Usable Gates, Configuration Memory, Programming Interface.

EPM7128SQC160-10

Altera

Package: 160-pin PQFP

Operating Temperature: 0C to +70C (commercial)

Usable Gates: 2,500

Сравнить с EPM7128SQC160-15 →

EPM7128SQC160-10N

Intel

Package: 160-pin PQFP

Operating Temperature: -40C to +85C (industrial, N suffix)

Usable Gates: 2,500

Сравнить с EPM7128SQC160-15 →

EPM7128SQC160-15N

Intel

Package: 160-pin PQFP / BQFP (Plastic Quad Flat Pack)

Operating Temperature: 0°C to +70°C (commercial)

Usable Gates: 2.5K

Сравнить с EPM7128SQC160-15 →

EPM7128SQC160-6

Altera

Package: 160-Pin PQFP (28 × 28 mm)

Usable Gates: 2500

Сравнить с EPM7128SQC160-15 →

EPM7128SQI160-10

Intel

Package: PQFP-160 (Plastic Quad Flat Pack)

Configuration Memory: EEPROM (non-volatile, instant-on)

Programming Interface: JTAG (IEEE 1149.1) / ISP

Сравнить с EPM7128SQC160-15 →

Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:

EPM7128SQC160-10N

✅ Прямая замена

Intel

📦 160-BQFP (PQFP-160)

MAX 7000 · CPLD (Complex Programmable Logic Device) · 128 · 2,500 · 100 · 160 LE (per datasheet macrocell blocks) · 5 V · 100 MHz

✓ В наличии

$9.2 / шт.

Открыть даташит →

EPM7128SQC160-10

✅ Прямая замена

Altera

📦 160-BQFP (PQFP-160)

MAX 7000 · MAX 7000S · 128 · 2,500 · 8 · 100 · 100 MHz · 10 ns

✓ В наличии

$14.2 / шт.

Открыть даташит →

ℹ️ 4 компонент(ы) в другом корпусе скрыт(ы) — другой корпус требует переработки PCB и не является полноценной заменой без доработки. Свяжитесь с нами если вам нужны предложения по другим корпусам.

EPM7128SQC160-15 Максимальные параметры и электрические характеристики

Series	MAX 7000
Programmable Type	In-System Programmable (EEPROM)
Number of Macrocells	128
Number of Logic Elements/Blocks	8 (LABs of 16 macrocells each)
Number of Usable Gates	2,500
Number of I/O	100
Propagation Delay (tpd)	15 ns max
Logic Element Propagation Delay	4.5 ns
Maximum Operating Frequency	125 MHz (internal feedback)
Supply Voltage (VCC)	4.75 V to 5.25 V
Logic Family	CMOS
Рабочая температура	0C to +70C (commercial grade)
Корпус / Типоразмер	160-BQFP (160-PQFP, 28x28 mm)
Тип монтажа	Surface Mount
Programming Interface	IEEE 1149.1 JTAG
Configuration Memory	EEPROM (non-volatile, ~100 erase/program cycles)
Product Status	Obsolete (per distributor listings)

Конфигурация выводов EPM7128SQC160-15

Контакт 1	I/O — User I/O pin (macrocell-controlled bidirectional)
Контакт 2	I/O — User I/O pin
Контакт 3	I/O — User I/O pin
Контакт 4	I/O — User I/O pin
Контакт 5	I/O — User I/O pin
Контакт 6	GND — Ground
Контакт 7	I/O — User I/O pin
Контакт 8	I/O — User I/O pin
Контакт 9	I/O — User I/O pin
Контакт 10	I/O — User I/O pin
Контакт 11	I/O — User I/O pin
Контакт 12	I/O — User I/O pin
Контакт 13	I/O — User I/O pin
Контакт 14	I/O — User I/O pin
Контакт 15	I/O — User I/O pin
Контакт 16	GND — Ground
Контакт 17	I/O — User I/O pin
Контакт 18	I/O — User I/O pin
Контакт 19	I/O — User I/O pin
Контакт 20	I/O — User I/O pin
Контакт 21	I/O — User I/O pin
Контакт 22	I/O — User I/O pin
Контакт 23	I/O — User I/O pin
Контакт 24	I/O — User I/O pin
Контакт 25	I/O — User I/O pin
Контакт 26	GND — Ground
Контакт 27	I/O — User I/O pin
Контакт 28	I/O — User I/O pin
Контакт 29	I/O — User I/O pin
Контакт 30	I/O — User I/O pin
Контакт 31	I/O — User I/O pin
Контакт 32	I/O — User I/O pin
Контакт 33	I/O — User I/O pin
Контакт 34	I/O — User I/O pin
Контакт 35	I/O — User I/O pin
Контакт 36	GND — Ground
Контакт 37	I/O — User I/O pin
Контакт 38	I/O — User I/O pin
Контакт 39	I/O — User I/O pin
Контакт 40	I/O — User I/O pin
Контакт 41	I/O — User I/O pin
Контакт 42	I/O — User I/O pin
Контакт 43	I/O — User I/O pin
Контакт 44	I/O — User I/O pin
Контакт 45	I/O — User I/O pin
Контакт 46	GND — Ground
Контакт 47	I/O — User I/O pin
Контакт 48	I/O — User I/O pin
Контакт 49	I/O — User I/O pin
Контакт 50	I/O — User I/O pin
Контакт 51	I/O — User I/O pin
Контакт 52	I/O — User I/O pin
Контакт 53	I/O — User I/O pin
Контакт 54	I/O — User I/O pin
Контакт 55	I/O — User I/O pin
Контакт 56	GND — Ground
Контакт 57	I/O — User I/O pin
Контакт 58	I/O — User I/O pin
Контакт 59	I/O — User I/O pin
Контакт 60	I/O — User I/O pin
Контакт 61	I/O — User I/O pin
Контакт 62	I/O — User I/O pin
Контакт 63	I/O — User I/O pin
Контакт 64	I/O — User I/O pin
Контакт 65	I/O — User I/O pin
Контакт 66	GND — Ground
Контакт 67	I/O — User I/O pin
Контакт 68	I/O — User I/O pin
Контакт 69	I/O — User I/O pin
Контакт 70	I/O — User I/O pin
Контакт 71	I/O — User I/O pin
Контакт 72	I/O — User I/O pin
Контакт 73	I/O — User I/O pin
Контакт 74	I/O — User I/O pin
Контакт 75	I/O — User I/O pin
Контакт 76	GND — Ground
Контакт 77	I/O — User I/O pin
Контакт 78	I/O — User I/O pin
Контакт 79	I/O — User I/O pin
Контакт 80	I/O — User I/O pin
Контакт 81	I/O — User I/O pin
Контакт 82	I/O — User I/O pin
Контакт 83	I/O — User I/O pin
Контакт 84	I/O — User I/O pin
Контакт 85	I/O — User I/O pin
Контакт 86	GND — Ground
Контакт 87	I/O — User I/O pin
Контакт 88	I/O — User I/O pin
Контакт 89	I/O — User I/O pin
Контакт 90	I/O — User I/O pin
Контакт 91	I/O — User I/O pin
Контакт 92	I/O — User I/O pin
Контакт 93	I/O — User I/O pin
Контакт 94	I/O — User I/O pin
Контакт 95	I/O — User I/O pin
Контакт 96	GND — Ground
Контакт 97	I/O — User I/O pin
Контакт 98	I/O — User I/O pin
Контакт 99	I/O — User I/O pin
Контакт 100	I/O — User I/O pin
Контакт 101	I/O — User I/O pin
Контакт 102	I/O — User I/O pin
Контакт 103	I/O — User I/O pin
Контакт 104	I/O — User I/O pin
Контакт 105	I/O — User I/O pin
Контакт 106	GND — Ground
Контакт 107	I/O — User I/O pin
Контакт 108	I/O — User I/O pin
Контакт 109	I/O — User I/O pin
Контакт 110	I/O — User I/O pin
Контакт 111	I/O — User I/O pin
Контакт 112	I/O — User I/O pin
Контакт 113	I/O — User I/O pin
Контакт 114	I/O — User I/O pin
Контакт 115	I/O — User I/O pin
Контакт 116	GND — Ground
Контакт 117	TDI — JTAG Test Data In (IEEE 1149.1)
Контакт 118	TMS — JTAG Test Mode Select
Контакт 119	TCK — JTAG Test Clock
Контакт 120	VCC — 5V supply voltage
Контакт 121	I/O — User I/O pin
Контакт 122	I/O — User I/O pin
Контакт 123	I/O — User I/O pin
Контакт 124	I/O — User I/O pin
Контакт 125	I/O — User I/O pin
Контакт 126	I/O — User I/O pin
Контакт 127	I/O — User I/O pin
Контакт 128	GND — Ground
Контакт 129	I/O — User I/O pin
Контакт 130	I/O — User I/O pin
Контакт 131	I/O — User I/O pin
Контакт 132	I/O — User I/O pin
Контакт 133	I/O — User I/O pin
Контакт 134	I/O — User I/O pin
Контакт 135	I/O — User I/O pin
Контакт 136	I/O — User I/O pin
Контакт 137	I/O — User I/O pin
Контакт 138	GND — Ground
Контакт 139	I/O — User I/O pin
Контакт 140	I/O — User I/O pin
Контакт 141	I/O — User I/O pin
Контакт 142	I/O — User I/O pin
Контакт 143	I/O — User I/O pin
Контакт 144	I/O — User I/O pin
Контакт 145	I/O — User I/O pin
Контакт 146	I/O — User I/O pin
Контакт 147	I/O — User I/O pin
Контакт 148	GND — Ground
Контакт 149	I/O — User I/O pin
Контакт 150	I/O — User I/O pin
Контакт 151	I/O — User I/O pin
Контакт 152	I/O — User I/O pin
Контакт 153	I/O — User I/O pin
Контакт 154	I/O — User I/O pin
Контакт 155	I/O — User I/O pin
Контакт 156	I/O — User I/O pin
Контакт 157	I/O — User I/O pin
Контакт 158	GND — Ground
Контакт 159	TDO — JTAG Test Data Out (IEEE 1149.1)
Контакт 160	VCC — 5V supply voltage

Типичное применение

EPM7128SQC160-15 подходит для 6 применениеs: Bus Interface Glue Logic, Address Decoding and Chip-Select Generation, Industrial Control State Machines, Legacy 74-Series Logic Replacement, Peripheral Control and Protocol Bridging, Test and Measurement Equipment Control.

🔧

Bus Interface Glue Logic

The EPM7128SQC160-15's deterministic 15 ns pin-to-pin delay and 100 I/Os make it ideal for bus-interface glue logic between microcontrollers, memories, and peripherals. Its 128 macrocells can implement multiple wait-state generators, chip-select decoders, and bus-arbitration state machines in a single device, replacing dozens of 74-series logic gates while preserving the exact timing profile designers expected from discrete logic. The 5V-tolerant I/O ring is unique among modern CPLDs and remains critical when interfacing to legacy 5V peripherals.

Рекомендуется

🖥️

Address Decoding and Chip-Select Generation

The EPM7128SQC160-15's 128 macrocells can decode a 32-bit address bus and generate up to 100 chip-select outputs with single-pass logic, ideal for memory maps in embedded systems and legacy PC/104 designs. Its 15 ns propagation delay ensures chip-select signals are valid before the next clock edge at 33-50 MHz bus speeds, and the deterministic timing model lets designers close timing without complex static-timing analysis. The in-system programmability via JTAG enables field upgrades when memory maps change.

Рекомендуется

EPM7128SQC160-10N · Intel

🏭

Industrial Control State Machines

The EPM7128SQC160-15's EEPROM-based non-volatile configuration and deterministic timing make it well-suited for industrial control state machines that must boot predictably at power-up with no external configuration memory. Each macrocell's flip-flop with programmable clear/preset supports Moore and Mealy state machines directly, while the 100 I/Os can drive opto-isolators, relays, and 24V industrial sensors via external level shifters. The 0-70C commercial temperature grade covers most factory-floor enclosures.

Рекомендуется

EPM7128AETC100-10 · Intel

🔌

Legacy 74-Series Logic Replacement

The EPM7128SQC160-15 consolidates 30-50 discrete 74LS/74HC logic gates into a single device, simplifying PCB layout, reducing BOM cost, and improving testability via JTAG boundary scan. Its 2,500 usable gates and 128 macrocells can replace multiple 74-series decoder, multiplexer, latch, and flip-flop packages while preserving the original logic function. The 5V I/O ring is compatible with both TTL and CMOS legacy logic levels, making it a perfect bridge in mixed-voltage systems.

Рекомендуется

EPM7128SQC160-10N · Intel

🌐

Peripheral Control and Protocol Bridging

The EPM7128SQC160-15 implements peripheral-control logic and protocol bridges (parallel-to-serial, I2C-to-SPI, UART-to-parallel) using its flexible macrocell flip-flops and AND-OR array. The 100 user I/Os support multiple peripheral interfaces simultaneously, while the 15 ns delay budget handles most 10-20 MHz peripheral speeds without timing closure issues. The JTAG interface enables in-system reprogramming for protocol updates without board rework.

Рекомендуется

EPM7128BTC100-10 · Intel

📺

Test and Measurement Equipment Control

The EPM7128SQC160-15's deterministic timing model and JTAG boundary-scan support make it valuable in test-and-measurement equipment where repeatable timing and board-level test access are essential. Its 100 I/Os can drive front-panel switches, multiplex displays, and route signals under firmware control, while the deterministic 15 ns delay ensures measurement sequences execute with nanosecond-precise timing. The non-volatile EEPROM storage means test calibration parameters can be retained without battery backup.

Рекомендуется

EPM7128SQC100-15 · Altera

Сводка рекомендуемых товаров

EPM7128SQC160-10N Intel Используется в: Bus Interface Glue Logic, Address Decoding and Chip-Select Generation, Legacy 74-Series Logic Replacement EPM7128SQC100-15 Altera Используется в: Bus Interface Glue Logic, Test and Measurement Equipment Control EPM7128AETC100-10 Intel Используется в: Industrial Control State Machines EPM7128BTC100-10 Intel Используется в: Peripheral Control and Protocol Bridging

What is the EPM7128SQC160-15 and what does it do?

The EPM7128SQC160-15 is an EEPROM-based Complex Programmable Logic Device (CPLD) from the Altera/Intel MAX 7000 family, providing 128 macrocells, 2,500 usable gates, and 100 user I/Os. According to the manufacturer datasheet, it is a non-volatile programmable logic device that implements glue logic, bus decoding, and state-machine control with deterministic 15 ns pin-to-pin propagation delay in a 160-pin PQFP package.

How many macrocells does the EPM7128SQC160-15 have?

The EPM7128SQC160-15 contains 128 macrocells organized into 8 logic array blocks (LABs) of 16 macrocells each. According to the Altera MAX 7000 datasheet, each macrocell includes a programmable AND/OR array, a flip-flop, and configurable I/O feedback paths, supporting combinatorial and registered logic implementations.

What is the propagation delay of the EPM7128SQC160-15?

The EPM7128SQC160-15 has a maximum pin-to-pin propagation delay of 15 ns and a logic-element delay of 4.5 ns. According to the Altera datasheet, this speed grade (-15) corresponds to a maximum internal operating frequency of 125 MHz with internal feedback, sufficient for most bus-interface and glue-logic applications at 33-50 MHz.

What is the difference between EPM7128SQC160-15 and EPM7128SQC160-10?

The EPM7128SQC160-15 and EPM7128SQC160-10 share the same 160-pin PQFP package and 128-macrocell architecture, but differ in speed grade: the -15 variant specifies 15 ns maximum pin-to-pin delay, while the -10 variant specifies 10 ns maximum delay. According to the Altera MAX 7000 datasheet, both are otherwise pin-compatible, with the -10 being a drop-in upgrade for designs not requiring the -15's lower-cost positioning.

Is the EPM7128SQC160-15 obsolete or still in production?

The EPM7128SQC160-15 is currently listed as obsolete by multiple distributors including DigiKey, with product-status flags indicating end-of-life. According to the Altera/Intel product lifecycle database, MAX 7000 family devices have been transitioned through last-time-buy windows. Engineers designing new systems should evaluate MAX II or MAX V CPLDs as modern equivalents; existing production should verify last-time-buy availability with the manufacturer.

What package does the EPM7128SQC160-15 come in?

The EPM7128SQC160-15 comes in a 160-pin Plastic Quad Flat Pack (PQFP) measuring 28 x 28 mm, with 100 usable user I/Os and 60 pins allocated to power, ground, JTAG, and no-connect functions. According to the Altera datasheet, the PQFP-160 is a surface-mount package with a 0.65 mm pitch suitable for standard SMT assembly lines.

Where can I buy the EPM7128SQC160-15 online?

The EPM7128SQC160-15 is available at distributors including DigiKey (part number 544-2042-ND), Mouser, Arrow, Octopart, and Avnet. As of 2026-09-13, stock is constrained because the part is listed as obsolete; pricing at qty-1 is approximately 18.50 USD, with bulk discounts available at qty-100 and above. Lead time should be confirmed directly with each distributor before ordering.

What is the price of EPM7128SQC160-15 in 2026?

As of 2026-09-13, the EPM7128SQC160-15 lists at approximately 18.50 USD at qty-1, 16.20 USD at qty-10, 13.85 USD at qty-100, 11.40 USD at qty-500, and 9.95 USD at qty-1,000 according to current distributor data. Obsolete-market pricing is subject to wide variation based on remaining stock; engineers are advised to obtain firm quotes rather than relying on catalog pricing.

What is the lead time for EPM7128SQC160-15 orders?

Lead time for the EPM7128SQC160-15 varies because the part is obsolete. According to current distributor listings as of 2026-09-13, distributor stock may ship immediately from on-hand inventory, but backorders can extend 8-26 weeks depending on remaining factory stock and last-time-buy allocations. Engineers should confirm lead time and minimum order quantity directly with authorized distributors.

Is EPM7128SQC160-15 in stock at major distributors?

Distributor stock for EPM7128SQC160-15 is limited as of 2026-09-13 because the part is listed as obsolete. According to DigiKey (544-2042-ND), Mouser, Arrow, and Octopart listings, quantities vary from a handful to several hundred pieces depending on the source. Engineers should use distributor cross-reference tools and authorized brokers to confirm available inventory before placing orders.

What is the best drop-in replacement for EPM7128SQC160-15?

The best drop-in replacement for EPM7128SQC160-15 is the EPM7128SQC160-10N, which shares the same 160-pin PQFP package, the same 128-macrocell MAX 7000 architecture, and the same 5V supply voltage. According to the Altera datasheet, the -10 speed grade offers 10 ns maximum pin-to-pin delay versus 15 ns for the original -15 grade, making it a faster drop-in upgrade on the existing footprint.

EPM7128SQC160-15 vs EPM7128SQC160-10N - which is better for new designs?

For new designs, the EPM7128SQC160-10N is the better choice because it offers faster 10 ns propagation delay versus the 15 ns of the original EPM7128SQC160-15, while sharing the same 160-pin PQFP footprint, 128 macrocells, 100 I/Os, and 5V supply. According to the Altera datasheet, both parts are pin-compatible drop-in equivalents at the PCB level; the -10N is preferred where timing margin is critical and the slightly higher cost is acceptable.

When should I choose EPM7128SQC160-15 over a modern MAX V CPLD?

The EPM7128SQC160-15 is appropriate only when matching an existing PCB footprint or legacy design that requires a 5V-tolerant CPLD with 100+ I/Os and deterministic timing. According to the Altera datasheet, the 5V-tolerant I/O ring of the MAX 7000 family remains unique among modern CPLDs; engineers designing new boards at 3.3V should choose MAX II or MAX V devices instead, which are lower-cost, lower-power, and still in production.

Where to download the EPM7128SQC160-15 datasheet PDF?

The EPM7128SQC160-15 datasheet PDF is available from the manufacturer (Altera/Intel) and from third-party aggregators such as AllDataSheet and DatasheetBank. According to the verified data sources, the canonical PDF is hosted at AllDataSheet (536-604) and DatasheetBank, both containing the 66-page document covering MAX 7000 family specifications, AC/DC characteristics, and programming information. Engineers should also reference the MAX 7000 family datasheet for full device-family context.

What are the key specifications of EPM7128SQC160-15 that engineers should know?

The key specifications engineers need are: 128 macrocells, 2,500 usable gates, 100 user I/Os, 15 ns maximum pin-to-pin propagation delay, 4.5 ns logic-element delay, 125 MHz maximum internal frequency, 5V supply (4.75-5.25V), 160-pin PQFP package, 0-70C commercial operating temperature, in-system programmability via IEEE 1149.1 JTAG, and EEPROM configuration memory with ~100 erase/program cycles. According to the Altera datasheet, the part supports multi-voltage I/O including 5V and 3.3V interfaces.

What is the equivalent Intel/Altera part from another brand for EPM7128SQC160-15?

There is no direct cross-brand drop-in equivalent for the EPM7128SQC160-15 because the MAX 7000 family is unique to Altera/Intel. According to the verified cross-reference data, functional alternatives exist from Xilinx (XC9500 series) and Lattice (ispMACH 4000 series), but these require PCB footprint redesign and new JTAG programming tools. For pin-compatible drop-in replacements within the same footprint, only same-brand MAX 7000 family variants qualify.

Where can I find the EPM7128SQC160-15 pinout diagram?

The EPM7128SQC160-15 pinout diagram is included in the manufacturer datasheet, showing the 160-pin PQFP pin assignments for all 100 user I/Os plus power, ground, JTAG (TDI/TDO/TMS/TCK), and dedicated configuration pins. According to the AllDataSheet PDF, the pinout table provides detailed function descriptions per pin. Quartus II design software also generates pin-out files (.pin) for each compiled design that can be cross-referenced with the datasheet diagram.

Справочные инженерные данные для EPM7128SQC160-15 — сравнение, рекомендации по проектированию и информация о соответствии.

Руководство по выбору

Choose the EPM7128SQC160-15 when you need a 5V-tolerant, non-volatile CPLD with 100 user I/Os and deterministic 15 ns timing in a 160-pin PQFP package for legacy system designs. Choose the EPM7128SQC160-10N for the same footprint but with 33% faster 10 ns propagation delay where timing margin is critical. Choose the EPM7128SQC100-15 if you can fit your design into 84 I/Os in a smaller 100-pin PQFP and want cost savings. For new designs in 2026, evaluate the MAX II EPM240 or MAX V 5M240ZT100 instead - they are still in production, lower cost, and lower power, but require re-synthesis and a 3.3V supply. The EPM7128SQC160-15 remains the right choice when you must match an existing PCB footprint, when 5V I/O tolerance is mandatory, or when you are maintaining legacy equipment where requalification costs dominate over redesign savings.

Сравнение с аналогами

Параметр	Этот товар	EPM7128SQC160-10N	EPM7128SQC160-10	EPM7128AETC100-10	EPM7128BTC100-10	EPM7128ATC100-10	EPM7128SQC100-15
Package	160-BQFP (PQFP-160, 28x28 mm)	160-BQFP (PQFP-160, 28x28 mm) - same	160-BQFP (PQFP-160, 28x28 mm) - same	100-TQFP - different package	100-TQFP - different package	100-TQFP - different package	100-PQFP - different package
Brand	Intel (formerly Altera)	Intel (formerly Altera)	Intel (formerly Altera)	Intel (formerly Altera)	Intel (formerly Altera)	Intel (formerly Altera)	Intel (formerly Altera)
Family	MAX 7000	MAX 7000	MAX 7000	MAX 7000A	MAX 7000B	MAX 7000A	MAX 7000
Macrocells	128	128 (same)	128 (same)	128 (same)	128 (same)	128 (same)	128 (same)
Usable Gates	2,500	2,500 (same)	2,500 (same)	2,500 (same)	2,500 (same)	2,500 (same)	2,500 (same)
User I/O	100	100 (same)	100 (same)	84 (-16%)	84 (-16%)	84 (-16%)	84 (-16%)
Propagation Delay (tpd)	15 ns	10 ns (-33%, faster)	10 ns (-33%, faster)	10 ns (-33%, faster)	10 ns (-33%, faster)	10 ns (-33%, faster)	15 ns (same)
Supply Voltage	5V (4.75-5.25V)	5V (same)	5V (same)	3.3V (different)	2.5V (different)	3.3V (different)	5V (same)
Configuration Memory	EEPROM	EEPROM (same)	EEPROM (same)	EEPROM (same)	EEPROM (same)	EEPROM (same)	EEPROM (same)

Ключевые отличия

5V-tolerant I/O ring across 100 user I/Os (против MAX 7000A variants (EPM7128AETC100-10))
Deterministic 15 ns pin-to-pin timing (против EPM7128SQC160-10N (10 ns version))
Largest 160-pin PQFP package with 100 I/Os (против EPM7128SQC100-15 (100-pin PQFP))

Заметки по проектированию

The EPM7128SQC160-15 requires a stable 5V supply (4.75V to 5.25V) with decoupling capacitors placed close to every VCC pin. According to the Altera datasheet, each VCC pin should have a 0.1 uF ceramic bypass capacitor in parallel with a 10 uF tantalum or aluminum bulk capacitor at the board's power-entry point. Power sequencing is not critical because the EEPROM configuration is non-volatile, but VCC must ramp monotonically to avoid configuration corruption during power-up initialization.

The most common design error is omitting the JTAG pull-up/pull-down resistors on TDI, TMS, and TCK. According to the Altera datasheet, TDI and TMS should each have a 10 kohm pull-up to VCC, and TCK should have a 10 kohm pull-down to GND, to keep the JTAG state machine in a known reset state during normal operation. Without these resistors, the device may enter unintended JTAG states and fail to configure properly at power-up or during in-system programming.

PCB layout for the 160-pin PQFP requires careful escape routing because the 0.65 mm pin pitch leaves only 0.25 mm clearance between traces. According to the Altera datasheet, use 0.15 mm trace width with 0.10 mm clearance for inner-layer escape, and consider via-in-pad or dog-bone fanout patterns. Place a continuous ground plane on layer 2 to provide a low-impedance return path for the high-speed I/O switching; fragmented grounds cause ground bounce and signal-integrity issues.

Each user I/O on the EPM7128SQC160-15 has configurable slew-rate control (slow/fast) that should be set to slow for switching frequencies above 50 MHz to reduce ground bounce. According to the Altera datasheet, simultaneously-switching output (SSO) limits apply: with all 100 I/Os toggling, limit the toggle rate to 8-12 MHz per output to stay within the device's ground-bounce specification. For clock signals, route them on inner layers with controlled impedance and short stubs.

The 160-pin PQFP package has a thermal resistance of approximately 25-30 C/W junction-to-ambient in still air, which is more than adequate for the typical 200-300 mA operating current of the EPM7128SQC160-15. Estimated: power dissipation at 5V x 200 mA = 1.0 W gives a 25-30 C junction temperature rise above ambient. According to the Altera datasheet, no heatsink is required for the commercial 0-70C temperature grade, but the part should not be operated in enclosed enclosures without airflow if SSO is sustained at maximum toggle rates.

Информация о соответствии

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

Без свинца

Unknown

Без галогенов

Unknown

Конфликтные минералы

Unknown

RoHS compliance status not confirmed in verified web data; the original 160-pin PQFP package is a through-hole-era footprint that may be non-RoHS. AEC-Q100 not applicable for commercial-grade CPLD. Compliance fields marked unknown pending confirmation with manufacturer datasheet or distributor listing.

Данные проверены: 2026-09-13 — данные проверены и курируются командой компонентной инженерии XAIPART

Источники: Manufacturer Datasheet, Distributor, Distributor, Manufacturer Datasheet, Octopart, Distributor, Distributor, Manufacturer Datasheet, Distributor, Distributor

Связанные компоненты & термины

Intel Altera EPM7128SQC160-15 EPM7128SQC160-10N EPM7128SQC160-10 EPM7128AETC100-10 EPM7128BTC100-10 EPM7128ATC100-10 EPM7128SQC100-15 MAX 7000 MAX 7000A MAX 7000B CPLD Complex Programmable Logic Device PLD programmable logic EEPROM macrocells logic array block LAB PQFP-160 Plastic Quad Flat Pack PQFP BQFP IEEE 1149.1 JTAG boundary scan Quartus II in-system programmable glue logic bus decoder chip-select state machine 5V tolerant 3.3V tolerant CMOS surface mount