EP1810JM-45 vs EP1810GM883 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JM-45 sa pamamagitan ng Altera at EP1810GM883 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JM-45 | EP1810GM883 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP1810 series) | — |
| Macrocells | 48 | 48 |
| Usable Gates | ~900 gates | — |
| Propagation Delay (tpd) | 45 ns (max, -45 speed grade) | 45 ns (max) |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-EPROM configuration | — |
| Package Type | JLCC-68 (ceramic J-leaded chip carrier) | — |
| Package Code | JM (windowed ceramic, UV-erasable) | — |
| Bilang ng Pin | 68 | — |
| Temperature na Operasyon | -55 C to +125 C (military grade) | -55C to +125C (MIL-STD-883 Class B) |
| I/O Compatibility | CMOS / TTL | — |
| Configuration Method | JEDEC fuse map, EPROM programmer | — |
| Programming Technology | UV-erasable EPROM (non-volatile, instant-on) | — |
| Uri ng Pagpapasok | Surface Mount (J-lead) | Through-Hole (PGA socket) |
| Logic Type | EPLD / PLD (programmable logic device) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status - legacy mil-spec part] | [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Family | — | Classic EPLD (EP1810 series) |
| Device Type | — | UV-Erasable Programmable Logic Device (EPLD) |
| Dedicated Inputs | — | 12 |
| User I/O Pins | — | 48 |
| Total Terminals | — | 68 |
| Global Clocks | — | 4 |
| Supply Voltage (Vcc) | — | 4.5 V to 5.5 V (nominal 5 V) |
| Maximum Toggle Frequency (fmax) | — | [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] |
| Process Technology | — | CMOS, UV-erasable |
| Packhaging | — | 68-Pin Ceramic Pin Grid Array (PGA) |
| Screening | — | MIL-STD-883 Class B (suffix '883' denotes MIL processing) |
| Lead-Free | — | [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] |