EP2SGX130GF40C4NGB vs EP2SGX130GF40C4NES Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2SGX130GF40C4NGB sa pamamagitan ng Intel at EP2SGX130GF40C4NES sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2SGX130GF40C4NGB EP2SGX130GF40C4NES
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Series Stratix II GX —
Family Enhanced Configuration (EPC) Devices Stratix II GX
Logic Elements 132,540 132,540
Logic Array Blocks (LABs) 6,627 —
User I/O Pins 734 734
Packhaging 1508-ball FBGA (GF40) —
Terminal Pitch 1.00 mm —
Speed Grade C4 C4 (speed grade -4)
Temperature Grade Commercial (0C to 85C) —
Transceivers Up to 20 multi-gigabit transceivers —
Max Transceiver Data Rate 6.375 Gbps —
PLLs 8 —
On-chip Memory TriMatrix memory (block RAM + distributed RAM) —
DSP Blocks Yes (embedded multipliers) Yes (variable, see datasheet)
Configuration Enhanced / EPC mode —
Tindminan RoHS [DATA_NEEDED: RoHS status] —
Logic Blocks / ALMs — Approximately 53,000 ALMs
Process Technology — 90 nm CMOS
Core Voltage — 1.2 V
Maximum Transceiver Data Rate — 6.375 Gbps
Transceiver Channels — Up to 20 (4 to 20, device-dependent)
Total Package Pins — 1508 (FC-FBGA ball grid)
Package Code — GF40 (FC-FBGA, 40x40 mm, 1.0 mm pitch)
Internal Operating Frequency — Up to 717 MHz
Embedded Memory — Approximately 4.5 Mbits (TriMatrix)
PLL Blocks — 8
Uri ng Pagpapasok — Surface Mount (flip-chip BGA)
Lead-Free / RoHS — Yes (LEAD FREE per datasheet family code)
Level ng MSL — Per JEDEC J-STD-020, typically MSL-4 or higher [DATA_NEEDED: exact MSL level]
Temperature na Operasyon — Commercial Extended (per N suffix)
JEDEC Standard Reference — MS-034AAU-1

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