EP3SE260H780C3 vs EP3SE260H780C3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE260H780C3 sa pamamagitan ng Intel at EP3SE260H780C3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP3SE260H780C3 | EP3SE260H780C3N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Device Family | Stratix III Enhanced (Stratix III E) | — |
| Series | EP3SE | Stratix® III E |
| Logic Elements | 255,000 | — |
| Logic Array Blocks (LABs) | 10200 | — |
| Embedded Memory | 16,672,768 bits (16.67 Mbit) | — |
| User I/Os | 488 | 488 |
| Operating Voltage (Core) | 0.9 V | — |
| Operating Voltage (Auxiliary) | 1.1 V | — |
| Process Technology | 65 nm CMOS | 40 nm CMOS |
| Speed Grade | C3 | — |
| Temperature na Operasyon | Commercial, 0C to +85C | 0 °C to +85 °C (C grade, commercial) |
| Maximum Core Frequency | 500 MHz | [DATA_NEEDED: maximum core frequency MHz] |
| Packhaging | 780-ball FCBGA (HBGA), flip-chip | 780-BBGA, FCBGA (H780) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 3 (168 hours) | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Packaging Type | Tray | — |
| Configuration Memory Support | Fast passive parallel, JTAG, Active Serial | — |
| Tindminan RoHS | Compliant (per product listings) | Compliant (lead-free 'N' suffix) |
| Logic Elements (LE) | — | 255,000 |
| Embedded Memory (bits) | — | 16,672,768 |
| Number of LABs/CLBs | — | 10,200 |
| Number of Pins / Balls | — | 780 |
| Supply Voltage (VCCINT) | — | [DATA_NEEDED: VCCINT nominal V] |
| Transceivers | — | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| DSP Blocks | — | [DATA_NEEDED: number of DSP blocks and precision] |
| Configuration Method | — | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | — | Altera Quartus II (legacy); Intel Quartus Prime |