EP3SE260H780C3 vs EP3SE260H780C3N 比較

詳細並排比較 EP3SE260H780C3 由 Intel 與 EP3SE260H780C3N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP3SE260H780C3 EP3SE260H780C3N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Device Family Stratix III Enhanced (Stratix III E) —
Series EP3SE Stratix® III E
Logic Elements 255,000 —
Logic Array Blocks (LABs) 10200 —
Embedded Memory 16,672,768 bits (16.67 Mbit) —
User I/Os 488 488
Operating Voltage (Core) 0.9 V —
Operating Voltage (Auxiliary) 1.1 V —
Process Technology 65 nm CMOS 40 nm CMOS
Speed Grade C3 —
工作溫度 Commercial, 0C to +85C 0 °C to +85 °C (C grade, commercial)
Maximum Core Frequency 500 MHz [DATA_NEEDED: maximum core frequency MHz]
封裝 780-ball FCBGA (HBGA), flip-chip 780-BBGA, FCBGA (H780)
安裝類型 Surface Mount (BGA) Surface Mount
濕度敏感等級 (MSL) 3 (168 hours) [DATA_NEEDED: MSL level per JEDEC J-STD-020]
Packaging Type Tray —
Configuration Memory Support Fast passive parallel, JTAG, Active Serial —
RoHS 狀態 Compliant (per product listings) Compliant (lead-free 'N' suffix)
Logic Elements (LE) — 255,000
Embedded Memory (bits) — 16,672,768
Number of LABs/CLBs — 10,200
Number of Pins / Balls — 780
Supply Voltage (VCCINT) — [DATA_NEEDED: VCCINT nominal V]
Transceivers — [DATA_NEEDED: number of embedded transceivers and max data rate]
DSP Blocks — [DATA_NEEDED: number of DSP blocks and precision]
Configuration Method — SRAM-based, configured via JTAG / passive / active serial / fast passive parallel
Design Toolchain — Altera Quartus II (legacy); Intel Quartus Prime

資料表與資源

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