EP3SL200H780C3N vs EP3SE260H780C3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL200H780C3N sa pamamagitan ng Intel at EP3SE260H780C3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP3SL200H780C3N | EP3SE260H780C3N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Aktibo |
| Family | Stratix III L (low-power) | — |
| Process Node | 40 nm | — |
| Logic Elements | 200,000 | — |
| Embedded Memory Bits | 10,901,504 bits | — |
| Logic Array Blocks (LABs) | 8,000 | — |
| User I/Os | 488 | 488 |
| Packhaging | 780-Ball FCBGA (HBGA), 29 x 29 mm | 780-BBGA, FCBGA (H780) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Maximum Internal Clock Frequency | 800 MHz | — |
| Transceivers | 24 channels, up to 3.75 Gbps | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| DSP Blocks | 384 | [DATA_NEEDED: number of DSP blocks and precision] |
| Speed Grade | C3 (commercial, -3 speed) | — |
| Temperature na Operasyon | 0C to +85C (commercial) | 0 °C to +85 °C (C grade, commercial) |
| Voltage - Core | 0.9 V / 1.0 V (core, VCC) | — |
| Voltage - I/O | 1.2 V to 3.3 V (VCCIO banks) | — |
| Level ng MSL | 3 | — |
| Lead-Free / RoHS | Yes | — |
| Mounting Pitch | 1.0 mm ball pitch | — |
| PLLs | 12 (Stratix III PLL array) | — |
| Configuration | JTAG IEEE Std 1149.1, passive/active serial | — |
| Series | — | Stratix® III E |
| Logic Elements (LE) | — | 255,000 |
| Embedded Memory (bits) | — | 16,672,768 |
| Number of LABs/CLBs | — | 10,200 |
| Number of Pins / Balls | — | 780 |
| Process Technology | — | 40 nm CMOS |
| Maximum Core Frequency | — | [DATA_NEEDED: maximum core frequency MHz] |
| Supply Voltage (VCCINT) | — | [DATA_NEEDED: VCCINT nominal V] |
| Tindminan RoHS | — | Compliant (lead-free 'N' suffix) |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Configuration Method | — | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | — | Altera Quartus II (legacy); Intel Quartus Prime |