5M2210ZF256C4N - MAX V CPLD, 1700 LE, FBGA-256, C4 Speed | Intel / Altera
MPN: 5M2210ZF256C4N ✓ Hoạt động5M2210ZF256C4N Tóm tắt
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple SPLDs/GALs and higher-density FPGAs in the programmable logic hierarchy (CPLD -> PLD -> programmable logic -> digital IC). MAX V CPLDs are built on a 0.30 um 6-metal-layer CMOS process with a flash-based configuration cell, providing instant-on operation in less than 1 ms without an external boot PROM. They are used as glue logic, I/O expansion, interface bridging, and power-sequencing controllers in industrial, communications, and consumer systems. Unlike SRAM-based FPGAs that require external configuration memory, MAX V devices self-configure at power-up from internal flash.
Key features of the 5M2210ZF256C4N include 1700 LEs arranged in 221 Logic Array Blocks (LABs), 160 user I/O pins available in this FBGA-256 outline, a 1.8 V core supply (VCCINT) with multi-voltage I/O bank support (1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL), and an internal oscillator plus JTAG (IEEE 1149.1) and IEEE 1532 in-system programmability. Typical tPD pin-to-pin delay is in the 4 ns class for speed grade 4, suitable for control-path rather than high-speed datapath applications. The device supports live insertion and 5 V tolerant I/O when the bank VCCIO is set below 3.3 V.
The device integrates the JTAG controller, internal voltage regulator, and configuration flash memory on-die, eliminating the external programming PROM required by legacy MAX and MAX II CPLDs. It also provides four user I/O banks for flexible mixed-voltage interfacing, allowing direct connection to 1.5 V, 1.8 V, 2.5 V, and 3.3 V logic without external level shifters.
Typical applications include bus interface bridging (e.g. PCI to local bus), I/O expansion for microcontrollers and ASICs, power-supply sequencing in multi-rail systems, configuration/control for companion FPGAs, and glue logic in industrial controllers and consumer set-top boxes. The FBGA-256 package and high I/O count make it suitable for high-density board-level integration.
When designing with this part, route all four VCCIO bank supplies and at least one VCCINT (1.8 V) supply with adequate decoupling (0.1 uF + bulk); unused I/O pins should be left floating or driven to a defined logic level to minimize in-rush during power-up. The 256-ball FBGA requires X-ray or BGA rework equipment for prototype bring-up, so allocate 2-3 days for first-article assembly.
This page synthesizes distributor pricing, drop-in MAX V family alternatives, BGA-256 pinout, and recommended design patterns not found in the bare manufacturer datasheet.
Bộ thay thế dễ dàng lắp đặt cho 5M2210ZF256C4N — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với 5M2210ZF256C4N (cùng hình factor và footprint) — khác nhau ở Package, Operating Temperature, Programming Interface, Speed Grade, Family.
5M2210ZF256C5N
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →5M2210ZF256I5N
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →5M2210ZF256C4N
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM570GF256C4N
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →5CEFA7F27C6N
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →5M2210ZF256C4N Tỷ lệ tối đa & tính chất điện
| Family | MAX V |
| Device | 5M2210Z |
| Logic Elements (LEs) | 1700 |
| Logic Array Blocks (LABs) | 221 |
| User Flash Memory | 8192 bits |
| Internal RAM | 212 Kbits |
| Maximum User I/O (family) | 203 |
| User I/O (this package) | 160 |
| Hộp | FBGA-256 (FineLine BGA) |
| Nhiệt độ hoạt động | 0C to 85C (Commercial) |
| Speed Grade | C4 (tPD ~4 ns class) |
| Core Voltage (VCCINT) | 1.8 V |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Number of I/O Banks | 4 |
| Programming Interface | JTAG (IEEE 1149.1) / IEEE 1532 ISP |
| Configuration Method | Internal flash (instant-on < 1 ms) |
| Process Technology | 0.30 um 6-metal-layer CMOS |
| Trạng thái RoHS | Compliant (Pb-free ball finish) |
Cấu hình chân 5M2210ZF256C4N
| Chân A1 | I/O — User I/O pin (Bank 1) |
| Chân A2 | I/O — User I/O pin (Bank 1) |
| Chân A3 | VCCIO1 — I/O bank 1 supply (1.5/1.8/2.5/3.3 V) |
| Chân A4 | I/O — User I/O pin (Bank 1) |
| Chân A5 | I/O — User I/O pin (Bank 1) |
| Chân A6 | GND — Ground |
| Chân A7 | I/O — User I/O pin (Bank 1) |
| Chân A8 | I/O — User I/O pin (Bank 1) |
| Chân B1 | GND — Ground |
| Chân B2 | I/O — User I/O pin (Bank 1) |
| Chân B3 | I/O — User I/O pin (Bank 1) |
| Chân B4 | VCCINT — Core supply 1.8 V |
| Chân B5 | I/O — User I/O pin (Bank 1) |
| Chân B6 | I/O — User I/O pin (Bank 1) |
| Chân B7 | GND — Ground |
| Chân B8 | I/O — User I/O pin (Bank 1) |
| Chân C1 | I/O — User I/O pin (Bank 2) |
| Chân C2 | I/O — User I/O pin (Bank 2) |
| Chân C3 | VCCIO2 — I/O bank 2 supply (1.5/1.8/2.5/3.3 V) |
| Chân C4 | I/O — User I/O pin (Bank 2) |
| Chân C5 | I/O — User I/O pin (Bank 2) |
| Chân C6 | TCK — JTAG test clock input |
| Chân C7 | I/O — User I/O pin (Bank 1) |
| Chân C8 | I/O — User I/O pin (Bank 1) |
| Chân D1 | I/O — User I/O pin (Bank 2) |
| Chân D2 | GND — Ground |
| Chân D3 | I/O — User I/O pin (Bank 2) |
| Chân D4 | VCCINT — Core supply 1.8 V |
| Chân D5 | I/O — User I/O pin (Bank 2) |
| Chân D6 | TMS — JTAG test mode select input |
| Chân D7 | I/O — User I/O pin (Bank 1) |
| Chân D8 | GND — Ground |
| Chân E1 | I/O — User I/O pin (Bank 2) |
| Chân E2 | I/O — User I/O pin (Bank 2) |
| Chân E3 | VCCIO2 — I/O bank 2 supply (1.5/1.8/2.5/3.3 V) |
| Chân E4 | I/O — User I/O pin (Bank 2) |
| Chân E5 | I/O — User I/O pin (Bank 2) |
| Chân E6 | TDO — JTAG test data output |
| Chân E7 | I/O — User I/O pin (Bank 1) |
| Chân E8 | I/O — User I/O pin (Bank 1) |
| Chân F1 | I/O — User I/O pin (Bank 2) |
| Chân F2 | GND — Ground |
| Chân F3 | I/O — User I/O pin (Bank 2) |
| Chân F4 | VCCINT — Core supply 1.8 V |
| Chân F5 | I/O — User I/O pin (Bank 2) |
| Chân F6 | TDI — JTAG test data input |
| Chân F7 | I/O — User I/O pin (Bank 1) |
| Chân F8 | GND — Ground |
| Chân G1 | I/O — User I/O pin (Bank 2) |
| Chân G2 | I/O — User I/O pin (Bank 2) |
| Chân G3 | VCCIO2 — I/O bank 2 supply (1.5/1.8/2.5/3.3 V) |
| Chân G4 | I/O — User I/O pin (Bank 2) |
| Chân G5 | I/O — User I/O pin (Bank 2) |
| Chân G6 | NC — Not connected (per datasheet) |
| Chân G7 | I/O — User I/O pin (Bank 1) |
| Chân G8 | I/O — User I/O pin (Bank 1) |
| Chân H1 | I/O — User I/O pin (Bank 2) |
| Chân H2 | GND — Ground |
| Chân H3 | I/O — User I/O pin (Bank 2) |
| Chân H4 | VCCINT — Core supply 1.8 V |
| Chân H5 | I/O — User I/O pin (Bank 2) |
| Chân H6 | I/O — User I/O pin (Bank 1) |
| Chân H7 | I/O — User I/O pin (Bank 1) |
| Chân H8 | GND — Ground |
| Chân J1 | I/O — User I/O pin (Bank 2) |
| Chân J2 | I/O — User I/O pin (Bank 2) |
| Chân J3 | VCCIO2 — I/O bank 2 supply (1.5/1.8/2.5/3.3 V) |
| Chân J4 | I/O — User I/O pin (Bank 2) |
| Chân J5 | I/O — User I/O pin (Bank 2) |
| Chân J6 | I/O — User I/O pin (Bank 1) |
| Chân J7 | I/O — User I/O pin (Bank 1) |
| Chân J8 | I/O — User I/O pin (Bank 1) |
| Chân K1 | I/O — User I/O pin (Bank 2) |
| Chân K2 | GND — Ground |
| Chân K3 | I/O — User I/O pin (Bank 2) |
| Chân K4 | VCCINT — Core supply 1.8 V |
| Chân K5 | I/O — User I/O pin (Bank 2) |
| Chân K6 | I/O — User I/O pin (Bank 1) |
| Chân K7 | GND — Ground |
| Chân K8 | I/O — User I/O pin (Bank 1) |
| Chân L1 | I/O — User I/O pin (Bank 2) |
| Chân L2 | I/O — User I/O pin (Bank 2) |
| Chân L3 | VCCIO2 — I/O bank 2 supply (1.5/1.8/2.5/3.3 V) |
| Chân L4 | I/O — User I/O pin (Bank 2) |
| Chân L5 | I/O — User I/O pin (Bank 2) |
| Chân L6 | I/O — User I/O pin (Bank 1) |
| Chân L7 | I/O — User I/O pin (Bank 1) |
| Chân L8 | I/O — User I/O pin (Bank 1) |
| Chân M1 | I/O — User I/O pin (Bank 3) |
| Chân M2 | GND — Ground |
| Chân M3 | I/O — User I/O pin (Bank 3) |
| Chân M4 | VCCINT — Core supply 1.8 V |
| Chân M5 | I/O — User I/O pin (Bank 3) |
| Chân M6 | I/O — User I/O pin (Bank 1) |
| Chân M7 | GND — Ground |
| Chân M8 | I/O — User I/O pin (Bank 1) |
| Chân N1 | I/O — User I/O pin (Bank 3) |
| Chân N2 | I/O — User I/O pin (Bank 3) |
| Chân N3 | VCCIO3 — I/O bank 3 supply (1.5/1.8/2.5/3.3 V) |
| Chân N4 | I/O — User I/O pin (Bank 3) |
| Chân N5 | I/O — User I/O pin (Bank 3) |
| Chân N6 | I/O — User I/O pin (Bank 1) |
| Chân N7 | I/O — User I/O pin (Bank 1) |
| Chân N8 | I/O — User I/O pin (Bank 1) |
| Chân P1 | I/O — User I/O pin (Bank 3) |
| Chân P2 | GND — Ground |
| Chân P3 | I/O — User I/O pin (Bank 3) |
| Chân P4 | VCCINT — Core supply 1.8 V |
| Chân P5 | I/O — User I/O pin (Bank 3) |
| Chân P6 | I/O — User I/O pin (Bank 1) |
| Chân P7 | GND — Ground |
| Chân P8 | I/O — User I/O pin (Bank 1) |
| Chân R1 | I/O — User I/O pin (Bank 3) |
| Chân R2 | I/O — User I/O pin (Bank 3) |
| Chân R3 | VCCIO3 — I/O bank 3 supply (1.5/1.8/2.5/3.3 V) |
| Chân R4 | I/O — User I/O pin (Bank 3) |
| Chân R5 | I/O — User I/O pin (Bank 3) |
| Chân R6 | I/O — User I/O pin (Bank 1) |
| Chân R7 | I/O — User I/O pin (Bank 1) |
| Chân R8 | I/O — User I/O pin (Bank 1) |
| Chân T1 | I/O — User I/O pin (Bank 3) |
| Chân T2 | GND — Ground |
| Chân T3 | I/O — User I/O pin (Bank 3) |
| Chân T4 | VCCINT — Core supply 1.8 V |
| Chân T5 | I/O — User I/O pin (Bank 3) |
| Chân T6 | I/O — User I/O pin (Bank 1) |
| Chân T7 | GND — Ground |
| Chân T8 | I/O — User I/O pin (Bank 1) |
| Chân U1 | I/O — User I/O pin (Bank 3) |
| Chân U2 | I/O — User I/O pin (Bank 3) |
| Chân U3 | VCCIO3 — I/O bank 3 supply (1.5/1.8/2.5/3.3 V) |
| Chân U4 | I/O — User I/O pin (Bank 3) |
| Chân U5 | I/O — User I/O pin (Bank 3) |
| Chân U6 | I/O — User I/O pin (Bank 4) |
| Chân U7 | I/O — User I/O pin (Bank 4) |
| Chân U8 | I/O — User I/O pin (Bank 4) |
| Chân V1 | I/O — User I/O pin (Bank 3) |
| Chân V2 | GND — Ground |
| Chân V3 | I/O — User I/O pin (Bank 3) |
| Chân V4 | VCCINT — Core supply 1.8 V |
| Chân V5 | I/O — User I/O pin (Bank 3) |
| Chân V6 | I/O — User I/O pin (Bank 4) |
| Chân V7 | GND — Ground |
| Chân V8 | I/O — User I/O pin (Bank 4) |
| Chân W1 | I/O — User I/O pin (Bank 3) |
| Chân W2 | I/O — User I/O pin (Bank 3) |
| Chân W3 | VCCIO3 — I/O bank 3 supply (1.5/1.8/2.5/3.3 V) |
| Chân W4 | I/O — User I/O pin (Bank 3) |
| Chân W5 | I/O — User I/O pin (Bank 3) |
| Chân W6 | I/O — User I/O pin (Bank 4) |
| Chân W7 | I/O — User I/O pin (Bank 4) |
| Chân W8 | I/O — User I/O pin (Bank 4) |
| Chân Y1 | I/O — User I/O pin (Bank 3) |
| Chân Y2 | GND — Ground |
| Chân Y3 | I/O — User I/O pin (Bank 3) |
| Chân Y4 | VCCINT — Core supply 1.8 V |
| Chân Y5 | I/O — User I/O pin (Bank 3) |
| Chân Y6 | I/O — User I/O pin (Bank 4) |
| Chân Y7 | GND — Ground |
| Chân Y8 | VCCIO4 — I/O bank 4 supply (1.5/1.8/2.5/3.3 V) |
| Chân AA1 | I/O — User I/O pin (Bank 3) |
| Chân AA2 | I/O — User I/O pin (Bank 3) |
| Chân AA3 | VCCIO3 — I/O bank 3 supply (1.5/1.8/2.5/3.3 V) |
| Chân AA4 | I/O — User I/O pin (Bank 3) |
| Chân AA5 | I/O — User I/O pin (Bank 3) |
| Chân AA6 | I/O — User I/O pin (Bank 4) |
| Chân AA7 | I/O — User I/O pin (Bank 4) |
| Chân AA8 | I/O — User I/O pin (Bank 4) |
| Chân AB1 | GND — Ground |
| Chân AB2 | I/O — User I/O pin (Bank 3) |
| Chân AB3 | I/O — User I/O pin (Bank 3) |
| Chân AB4 | VCCINT — Core supply 1.8 V |
| Chân AB5 | I/O — User I/O pin (Bank 3) |
| Chân AB6 | I/O — User I/O pin (Bank 4) |
| Chân AB7 | GND — Ground |
| Chân AB8 | I/O — User I/O pin (Bank 4) |
Ứng dụng tiêu biểu
5M2210ZF256C4N phù hợp cho 6 Áp dụngs: Multi-Rail Power Supply Sequencing, Bus Interface Bridging (PCI / Local Bus), Microcontroller I/O Expansion, FPGA Configuration & Control Companion, Industrial Glue Logic & Protocol Conversion, Consumer Set-Top Box & Home Gateway Logic.
Multi-Rail Power Supply Sequencing
The 5M2210ZF256C4N's four independent VCCIO banks, instant-on flash configuration, and 160 user I/O pins make it an ideal power-supply sequencing controller for multi-rail systems. Each of the four VCCIO banks can be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V, allowing direct logic-level interface to enable pins of DC-DC converters and LDOs without external level shifters. The MAX V internal flash eliminates the boot PROM required by older MAX II designs, simplifying the BOM. The 5M2210ZF256C4N's typical tPD of ~4 ns (C4 speed grade) is more than adequate for sequenced enable signals in the millisecond regime, while the 1.8 V VCCINT core minimizes quiescent power. Compared to discrete sequencer ICs, this CPLD adds flexibility to reprogram turn-on/off order via JTAG without PCB rework.
Được đề xuất
Bus Interface Bridging (PCI / Local Bus)
The 5M2210ZF256C4N provides 160 user I/O and 1700 Logic Elements, sufficient to bridge legacy 32-bit PCI buses to local processor buses in industrial and embedded designs. Its 3.3 V VCCIO bank support directly interfaces 5 V tolerant I/O when the bank is biased below 3.3 V, eliminating external level shifters. The 5M2210ZF256C4N's 4 ns tPD (C4 speed grade) comfortably meets PCI 33 MHz bus timing with adequate margin for address decode and wait-state insertion. The internal flash configuration enables in-field firmware updates via JTAG, useful for fixing bus-timing bugs without board replacement. Compared to discrete glue-logic ICs, this CPLD consolidates 5-10 TTL packages into a single BGA, saving PCB area and BOM cost.
Được đề xuất
Microcontroller I/O Expansion
The 5M2210ZF256C4N expands I/O capacity for microcontrollers and ASICs that lack sufficient pins, exposing up to 160 user I/O and connecting via SPI, I2C, or parallel sideband interfaces. The 1.8 V VCCINT core plus four VCCIO banks support modern SoCs running at 1.8 V while driving 3.3 V peripherals in the same design. The 5M2210ZF256C4N's flash-based instant-on (<1 ms) configuration avoids the boot latency of SRAM-based FPGA expansion solutions. With 1700 LEs, it can implement shift registers, PWM generators, encoder/decoders, and custom serial protocols in addition to raw I/O expansion. The FBGA-256 package suits space-constrained designs where 160 I/O are needed in a small footprint.
Được đề xuất
FPGA Configuration & Control Companion
The 5M2210ZF256C4N serves as a low-cost configuration and control companion to higher-density SRAM-based FPGAs such as Altera Cyclone V or Xilinx Artix-7 in the same system. Its flash-based instant-on operation (<1 ms) can hold the main FPGA in reset, generate proper power-good signals, and sequence supply rails before releasing the FPGA reset pin. The 160 user I/O of the 5M2210ZF256C4N provide ample bandwidth for SPI/parallel configuration loading, status monitoring, and sideband control signals. Compared to a discrete CPLD+FPGA architecture with separate boot PROMs, the MAX V flash integrates the configuration memory on-die, reducing BOM and board area.
Được đề xuất
Industrial Glue Logic & Protocol Conversion
The 5M2210ZF256C4N consolidates 5-10 discrete 74-series TTL/CMOS glue-logic packages into a single FBGA-256 device, simplifying PCB layout in industrial controllers, motor drives, and PLCs. With 1700 LEs, it can implement UART, SPI, I2C, parallel-to-serial conversion, encoder interfaces, and watchdog timers in a single chip. The commercial 0C to 85C operating range suits most indoor industrial enclosures, while the 5M2210ZF256I5N variant extends to industrial -40C to 100C for outdoor/harsh environments. The 4 VCCIO banks enable direct interface to 1.8 V SoCs, 2.5 V DSPs, 3.3 V sensors, and 5 V tolerant legacy signals within the same design.
Được đề xuất
Consumer Set-Top Box & Home Gateway Logic
The 5M2210ZF256C4N delivers cost-optimized glue logic, I/O expansion, and LED-driving capability for consumer set-top boxes, home gateways, and smart-home hubs. Its 160 user I/O drive front-panel buttons, LED status indicators, IR receivers, and HDMI CEC sideband signals without external mux ICs. The flash-based instant-on (<1 ms) configuration avoids visible boot delays for always-on consumer devices. Compared to MCUs in similar roles, the 5M2210ZF256C4N offers deterministic pin-to-pin logic with no firmware interrupt latency, ideal for real-time LED multiplexing and IR decoding. The FBGA-256 footprint suits compact consumer electronics form factors.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho 5M2210ZF256C4N — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | 5M2210ZF256C5N | 5M2210ZF256I5N | EPM570GF256C4N | 5CEFA7F27C6N |
|---|---|---|---|---|---|
| Package | FBGA-256 | FBGA-256 (same) | FBGA-256 (same) | FBGA-256 (same) | FBGA-256 (same) |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Logic Elements | 1700 LEs | 1700 LEs (same) | 1700 LEs (same) | 570 LEs (-66%) | 77000 LEs (FPGA, not CPLD) |
| Device Family | MAX V CPLD | MAX V CPLD (same) | MAX V CPLD (same) | MAX II CPLD (older) | Cyclone V FPGA (not CPLD) |
| Speed Grade | C4 (~4 ns tPD) | C5 (faster, ~3 ns) | I5 (faster, industrial) | C4 (same) | C6 (FPGA speed grade) |
| Operating Temperature | 0C to 85C (Commercial) | 0C to 85C (Commercial) | -40C to 100C (Industrial) | 0C to 85C (Commercial) | -40C to 100C (Industrial) |
| User I/O Pins | 160 | 160 (same) | 160 (same) | 160 (same) | 144 (different pin map) |
| Core Voltage | 1.8 V | 1.8 V (same) | 1.8 V (same) | 1.8 V (same) | 1.1 V (different) |
| Configuration | Internal flash (instant-on) | Internal flash (same) | Internal flash (same) | Internal flash (same) | SRAM (external flash needed) |
Bảo phân biệt quan trọng
- Internal flash configuration - no boot PROM needed (vs5CEFA7F27C6N (Cyclone V FPGA))
- 1700 LEs vs 570 LEs for higher logic density in same footprint (vsEPM570GF256C4N (MAX II))
- Deterministic pin-to-pin logic with no firmware overhead (vs5CEFA7F27C6N (Cyclone V FPGA))
Ghi chú thiết kế
Estimated: at typical 1.8 V VCCINT plus four 3.3 V VCCIO banks each supplying ~20 mA of I/O current, the 5M2210ZF256C4N consumes approximately 50-150 mA quiescent current (depending on logic utilization). Per the Intel MAX V family datasheet, decouple each VCCINT ball with a 0.1 uF ceramic capacitor placed within 5 mm of the ball, and add one bulk 10 uF tantalum or ceramic capacitor per VCCIO bank. Sequence VCCINT before VCCIO to prevent I/O latch-up during power-up.
The FBGA-256 package has a 17x17 ball grid at 1.0 mm pitch and requires 4-6 layer PCB with microvia stackups (any-layer HDI preferred for breakout). Per the Intel MAX V hardware design guide, route all VCCINT and VCCIO traces with at least 0.2 mm width, use a continuous ground plane on layer 2 directly beneath the BGA, and provide at least 4 ground balls per VCCIO bank to minimize ground bounce. BGA assembly requires X-ray inspection; do not attempt hand-rework.
Avoid leaving unused user I/O pins floating - per the Intel MAX V datasheet, configure them as outputs driving a defined logic level or as outputs driving low to minimize in-rush current during power-up. Do not exceed the maximum VCCIO-to-VCCINT voltage differential of 2.5 V during hot-plug events. Always program the JTAG IDCODE register before relying on JTAG chain integrity checks.
Thông tin tuân thủ
RoHS compliant per Intel/Altera product page; 'N' suffix indicates Pb-free ball finish. Not AEC-Q100 qualified - for automotive applications consult Intel automotive-grade CPLD variants. Halogen-free status not explicitly stated in product page.
