EPM9560RI240-20C - MAX 9000 560-Macrocell CPLD, 240-RQFP | Altera
MPN: EPM9560RI240-20C ✗ Cuối đờiEPM9560RI240-20C Tóm tắt
What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that combines the instant-on, deterministic timing of traditional PAL/GAL devices with much higher logic density. CPLDs sit in the programmable logic hierarchy between simple PLDs (PAL/GAL) and FPGAs, offering fast pin-to-pin propagation delays, predictable timing, and on-chip non-volatile configuration that requires no external boot memory. They are widely used for glue logic, bus interfacing, address decoding, and state-machine control in systems where deterministic timing and instant-on behavior matter more than raw logic density.
Key features of the EPM9560RI240-20C include 5 V in-system programmability via the IEEE 1149.1 JTAG boundary-scan test (BST) interface, support for 3.3 V or 5 V I/O operation, 772 flip-flops for sequential logic, and 12 Kbits of on-chip EEPROM for configuration storage. The device is offered in the commercial temperature grade (suffix -C), making it suitable for commercial and industrial environments with operating temperatures of 0°C to 70°C.
Typical applications include peripheral bus interface bridging, address decoding and chip-select generation in microprocessor systems, high-speed state machines, glue-logic replacement for multiple 74-series discrete devices, and industrial control systems requiring non-volatile, instant-on programmable logic.
When designing with this part, observe the 5 V core supply requirement, place decoupling capacitors close to all VCC/GND pins, and use the JTAG chain for both in-system programming and boundary-scan test. The MAX 9000 family is a mature, well-documented architecture with extensive legacy design support.
Bộ thay thế dễ dàng lắp đặt cho EPM9560RI240-20C — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EPM9560RI240-20C (cùng hình factor và footprint) — khác nhau ở Package, Programming Interface, Macrocells, Device Type, Process Technology.
EPM9560RI240-20
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM9560RI240-15C
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
EPM9560RI240-10
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM9480RC240-20
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EPM9480RC240-20C
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
EPM9560RI240-20C Tỷ lệ tối đa & tính chất điện
| Family | MAX 9000 |
| Device Type | EE PLD (CPLD) |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| User I/Os | 191 |
| Internal Operating Frequency | 100 MHz |
| Propagation Delay (tPD) | 20 ns (speed grade -20) |
| Supply Voltage (VCCINT) | 5 V |
| I/O Voltage | 3.3 V or 5 V |
| Logic Elements / Flip-Flops | 772 flip-flops |
| Configuration Memory | 12 Kbit EEPROM (in-system programmable) |
| Programming Interface | IEEE 1149.1 JTAG BST |
| Nhiệt độ hoạt động | 0°C to +70°C (commercial grade) |
| Hộp | 240-pin RQFP (Power Quad Flat Pack) |
| Process Technology | CMOS, EEPROM-based |
Cấu hình chân EPM9560RI240-20C
| Chân 1 | I/O — User I/O pin (bank 1) |
| Chân 2 | I/O — User I/O pin (bank 1) |
| Chân 3 | I/O — User I/O pin (bank 1) |
| Chân 4 | I/O — User I/O pin (bank 1) |
| Chân 5 | GND — Ground |
| Chân 6 | I/O — User I/O pin (bank 1) |
| Chân 7 | I/O — User I/O pin (bank 1) |
| Chân 8 | I/O — User I/O pin (bank 1) |
| Chân 9 | I/O — User I/O pin (bank 1) |
| Chân 10 | VCC — 5 V core supply |
| Chân 11 | I/O — User I/O pin (bank 2) |
| Chân 12 | I/O — User I/O pin (bank 2) |
| Chân 13 | I/O — User I/O pin (bank 2) |
| Chân 14 | I/O — User I/O pin (bank 2) |
| Chân 15 | I/O — User I/O pin (bank 2) |
| Chân 16 | I/O — User I/O pin (bank 2) |
| Chân 17 | GND — Ground |
| Chân 18 | I/O — User I/O pin (bank 2) |
| Chân 19 | I/O — User I/O pin (bank 2) |
| Chân 20 | I/O — User I/O pin (bank 2) |
| Chân 21 | I/O — User I/O pin (bank 2) |
| Chân 22 | VCC — 5 V core supply |
| Chân 23 | I/O — User I/O pin (bank 3) |
| Chân 24 | I/O — User I/O pin (bank 3) |
| Chân 25 | I/O — User I/O pin (bank 3) |
| Chân 26 | I/O — User I/O pin (bank 3) |
| Chân 27 | I/O — User I/O pin (bank 3) |
| Chân 28 | GND — Ground |
| Chân 29 | I/O — User I/O pin (bank 3) |
| Chân 30 | I/O — User I/O pin (bank 3) |
| Chân 31 | I/O — User I/O pin (bank 3) |
| Chân 32 | I/O — User I/O pin (bank 3) |
| Chân 33 | I/O — User I/O pin (bank 3) |
| Chân 34 | VCC — 5 V core supply |
| Chân 35 | I/O — User I/O pin (bank 4) |
| Chân 36 | I/O — User I/O pin (bank 4) |
| Chân 37 | I/O — User I/O pin (bank 4) |
| Chân 38 | I/O — User I/O pin (bank 4) |
| Chân 39 | GND — Ground |
| Chân 40 | I/O — User I/O pin (bank 4) |
| Chân 41 | I/O — User I/O pin (bank 4) |
| Chân 42 | I/O — User I/O pin (bank 4) |
| Chân 43 | I/O — User I/O pin (bank 4) |
| Chân 44 | I/O — User I/O pin (bank 4) |
| Chân 45 | VCC — 5 V core supply |
| Chân 46 | I/O — User I/O pin (bank 5) |
| Chân 47 | I/O — User I/O pin (bank 5) |
| Chân 48 | I/O — User I/O pin (bank 5) |
| Chân 49 | I/O — User I/O pin (bank 5) |
| Chân 50 | GND — Ground |
| Chân 51 | I/O — User I/O pin (bank 5) |
| Chân 52 | I/O — User I/O pin (bank 5) |
| Chân 53 | I/O — User I/O pin (bank 5) |
| Chân 54 | I/O — User I/O pin (bank 5) |
| Chân 55 | I/O — User I/O pin (bank 5) |
| Chân 56 | VCC — 5 V core supply |
| Chân 57 | I/O — User I/O pin (bank 6) |
| Chân 58 | I/O — User I/O pin (bank 6) |
| Chân 59 | I/O — User I/O pin (bank 6) |
| Chân 60 | I/O — User I/O pin (bank 6) |
| Chân 61 | GND — Ground |
| Chân 62 | I/O — User I/O pin (bank 6) |
| Chân 63 | I/O — User I/O pin (bank 6) |
| Chân 64 | I/O — User I/O pin (bank 6) |
| Chân 65 | I/O — User I/O pin (bank 6) |
| Chân 66 | I/O — User I/O pin (bank 6) |
| Chân 67 | VCC — 5 V core supply |
| Chân 68 | I/O — User I/O pin (bank 7) |
| Chân 69 | I/O — User I/O pin (bank 7) |
| Chân 70 | I/O — User I/O pin (bank 7) |
| Chân 71 | I/O — User I/O pin (bank 7) |
| Chân 72 | GND — Ground |
| Chân 73 | I/O — User I/O pin (bank 7) |
| Chân 74 | I/O — User I/O pin (bank 7) |
| Chân 75 | I/O — User I/O pin (bank 7) |
| Chân 76 | I/O — User I/O pin (bank 7) |
| Chân 77 | I/O — User I/O pin (bank 7) |
| Chân 78 | VCC — 5 V core supply |
| Chân 79 | I/O — User I/O pin (bank 8) |
| Chân 80 | I/O — User I/O pin (bank 8) |
| Chân 81 | I/O — User I/O pin (bank 8) |
| Chân 82 | I/O — User I/O pin (bank 8) |
| Chân 83 | GND — Ground |
| Chân 84 | I/O — User I/O pin (bank 8) |
| Chân 85 | I/O — User I/O pin (bank 8) |
| Chân 86 | I/O — User I/O pin (bank 8) |
| Chân 87 | I/O — User I/O pin (bank 8) |
| Chân 88 | I/O — User I/O pin (bank 8) |
| Chân 89 | VCC — 5 V core supply |
| Chân 90 | I/O — User I/O pin (bank 9) |
| Chân 91 | I/O — User I/O pin (bank 9) |
| Chân 92 | I/O — User I/O pin (bank 9) |
| Chân 93 | I/O — User I/O pin (bank 9) |
| Chân 94 | GND — Ground |
| Chân 95 | I/O — User I/O pin (bank 9) |
| Chân 96 | I/O — User I/O pin (bank 9) |
| Chân 97 | I/O — User I/O pin (bank 9) |
| Chân 98 | I/O — User I/O pin (bank 9) |
| Chân 99 | I/O — User I/O pin (bank 9) |
| Chân 100 | VCC — 5 V core supply |
| Chân 101 | I/O — User I/O pin (bank 10) |
| Chân 102 | I/O — User I/O pin (bank 10) |
| Chân 103 | I/O — User I/O pin (bank 10) |
| Chân 104 | I/O — User I/O pin (bank 10) |
| Chân 105 | GND — Ground |
| Chân 106 | I/O — User I/O pin (bank 10) |
| Chân 107 | I/O — User I/O pin (bank 10) |
| Chân 108 | I/O — User I/O pin (bank 10) |
| Chân 109 | I/O — User I/O pin (bank 10) |
| Chân 110 | I/O — User I/O pin (bank 10) |
| Chân 111 | VCC — 5 V core supply |
| Chân 112 | I/O — User I/O pin (bank 11) |
| Chân 113 | I/O — User I/O pin (bank 11) |
| Chân 114 | I/O — User I/O pin (bank 11) |
| Chân 115 | I/O — User I/O pin (bank 11) |
| Chân 116 | GND — Ground |
| Chân 117 | I/O — User I/O pin (bank 11) |
| Chân 118 | I/O — User I/O pin (bank 11) |
| Chân 119 | I/O — User I/O pin (bank 11) |
| Chân 120 | I/O — User I/O pin (bank 11) |
| Chân 121 | I/O — User I/O pin (bank 11) |
| Chân 122 | VCC — 5 V core supply |
| Chân 123 | I/O — User I/O pin (bank 12) |
| Chân 124 | I/O — User I/O pin (bank 12) |
| Chân 125 | I/O — User I/O pin (bank 12) |
| Chân 126 | I/O — User I/O pin (bank 12) |
| Chân 127 | GND — Ground |
| Chân 128 | I/O — User I/O pin (bank 12) |
| Chân 129 | I/O — User I/O pin (bank 12) |
| Chân 130 | I/O — User I/O pin (bank 12) |
| Chân 131 | I/O — User I/O pin (bank 12) |
| Chân 132 | I/O — User I/O pin (bank 12) |
| Chân 133 | VCC — 5 V core supply |
| Chân 134 | I/O — User I/O pin (bank 13) |
| Chân 135 | I/O — User I/O pin (bank 13) |
| Chân 136 | I/O — User I/O pin (bank 13) |
| Chân 137 | I/O — User I/O pin (bank 13) |
| Chân 138 | GND — Ground |
| Chân 139 | I/O — User I/O pin (bank 13) |
| Chân 140 | I/O — User I/O pin (bank 13) |
| Chân 141 | I/O — User I/O pin (bank 13) |
| Chân 142 | I/O — User I/O pin (bank 13) |
| Chân 143 | I/O — User I/O pin (bank 13) |
| Chân 144 | VCC — 5 V core supply |
| Chân 145 | I/O — User I/O pin (bank 14) |
| Chân 146 | I/O — User I/O pin (bank 14) |
| Chân 147 | I/O — User I/O pin (bank 14) |
| Chân 148 | I/O — User I/O pin (bank 14) |
| Chân 149 | GND — Ground |
| Chân 150 | I/O — User I/O pin (bank 14) |
| Chân 151 | I/O — User I/O pin (bank 14) |
| Chân 152 | I/O — User I/O pin (bank 14) |
| Chân 153 | I/O — User I/O pin (bank 14) |
| Chân 154 | I/O — User I/O pin (bank 14) |
| Chân 155 | VCC — 5 V core supply |
| Chân 156 | I/O — User I/O pin (bank 15) |
| Chân 157 | I/O — User I/O pin (bank 15) |
| Chân 158 | I/O — User I/O pin (bank 15) |
| Chân 159 | I/O — User I/O pin (bank 15) |
| Chân 160 | GND — Ground |
| Chân 161 | I/O — User I/O pin (bank 15) |
| Chân 162 | I/O — User I/O pin (bank 15) |
| Chân 163 | I/O — User I/O pin (bank 15) |
| Chân 164 | I/O — User I/O pin (bank 15) |
| Chân 165 | I/O — User I/O pin (bank 15) |
| Chân 166 | VCC — 5 V core supply |
| Chân 167 | I/O — User I/O pin (bank 16) |
| Chân 168 | I/O — User I/O pin (bank 16) |
| Chân 169 | I/O — User I/O pin (bank 16) |
| Chân 170 | I/O — User I/O pin (bank 16) |
| Chân 171 | GND — Ground |
| Chân 172 | I/O — User I/O pin (bank 16) |
| Chân 173 | I/O — User I/O pin (bank 16) |
| Chân 174 | I/O — User I/O pin (bank 16) |
| Chân 175 | I/O — User I/O pin (bank 16) |
| Chân 176 | I/O — User I/O pin (bank 16) |
| Chân 177 | VCC — 5 V core supply |
| Chân 178 | I/O — User I/O pin (bank 17) |
| Chân 179 | I/O — User I/O pin (bank 17) |
| Chân 180 | I/O — User I/O pin (bank 17) |
| Chân 181 | I/O — User I/O pin (bank 17) |
| Chân 182 | GND — Ground |
| Chân 183 | I/O — User I/O pin (bank 17) |
| Chân 184 | I/O — User I/O pin (bank 17) |
| Chân 185 | I/O — User I/O pin (bank 17) |
| Chân 186 | I/O — User I/O pin (bank 17) |
| Chân 187 | I/O — User I/O pin (bank 17) |
| Chân 188 | VCC — 5 V core supply |
| Chân 189 | I/O — User I/O pin (bank 18) |
| Chân 190 | I/O — User I/O pin (bank 18) |
| Chân 191 | I/O — User I/O pin (bank 18) |
| Chân 192 | I/O — User I/O pin (bank 18) |
| Chân 193 | GND — Ground |
| Chân 194 | I/O — User I/O pin (bank 18) |
| Chân 195 | I/O — User I/O pin (bank 18) |
| Chân 196 | I/O — User I/O pin (bank 18) |
| Chân 197 | I/O — User I/O pin (bank 18) |
| Chân 198 | I/O — User I/O pin (bank 18) |
| Chân 199 | VCC — 5 V core supply |
| Chân 200 | I/O — User I/O pin (bank 19) |
| Chân 201 | I/O — User I/O pin (bank 19) |
| Chân 202 | I/O — User I/O pin (bank 19) |
| Chân 203 | I/O — User I/O pin (bank 19) |
| Chân 204 | GND — Ground |
| Chân 205 | I/O — User I/O pin (bank 19) |
| Chân 206 | I/O — User I/O pin (bank 19) |
| Chân 207 | I/O — User I/O pin (bank 19) |
| Chân 208 | I/O — User I/O pin (bank 19) |
| Chân 209 | I/O — User I/O pin (bank 19) |
| Chân 210 | VCC — 5 V core supply |
| Chân 211 | I/O — User I/O pin (bank 20) |
| Chân 212 | I/O — User I/O pin (bank 20) |
| Chân 213 | I/O — User I/O pin (bank 20) |
| Chân 214 | I/O — User I/O pin (bank 20) |
| Chân 215 | GND — Ground |
| Chân 216 | I/O — User I/O pin (bank 20) |
| Chân 217 | I/O — User I/O pin (bank 20) |
| Chân 218 | I/O — User I/O pin (bank 20) |
| Chân 219 | I/O — User I/O pin (bank 20) |
| Chân 220 | I/O — User I/O pin (bank 20) |
| Chân 221 | VCC — 5 V core supply |
| Chân 222 | I/O — User I/O pin (bank 21) |
| Chân 223 | I/O — User I/O pin (bank 21) |
| Chân 224 | I/O — User I/O pin (bank 21) |
| Chân 225 | I/O — User I/O pin (bank 21) |
| Chân 226 | GND — Ground |
| Chân 227 | I/O — User I/O pin (bank 21) |
| Chân 228 | I/O — User I/O pin (bank 21) |
| Chân 229 | I/O — User I/O pin (bank 21) |
| Chân 230 | I/O — User I/O pin (bank 21) |
| Chân 231 | I/O — User I/O pin (bank 21) |
| Chân 232 | VCC — 5 V core supply |
| Chân 233 | I/O — User I/O pin (bank 22) |
| Chân 234 | I/O — User I/O pin (bank 22) |
| Chân 235 | I/O — User I/O pin (bank 22) |
| Chân 236 | I/O — User I/O pin (bank 22) |
| Chân 237 | GND — Ground |
| Chân 238 | I/O — User I/O pin (bank 22) |
| Chân 239 | TDI — JTAG Test Data Input |
| Chân 240 | TMS — JTAG Test Mode Select |
Ứng dụng tiêu biểu
EPM9560RI240-20C phù hợp cho 6 Áp dụngs: Microprocessor Glue Logic, Peripheral Bus Interface Bridging, Address Decoding and Chip Select Generation, High-Speed State Machine Controllers, Industrial Control and Instrumentation, Legacy System Modernization.
Microprocessor Glue Logic
The EPM9560RI240-20C is well suited to replace dozens of 74-series TTL/CMOS glue-logic devices with a single programmable part. Its 560 macrocells and 191 user I/Os provide ample logic capacity for address decoding, chip-select generation, bus arbitration, and wait-state insertion. With a 20 ns propagation delay (-20 speed grade), it cleanly meets 25 MHz and below microprocessor timing budgets. The 5 V core and 3.3 V/5 V I/O compatibility make it ideal for legacy 5 V microprocessor boards where deterministic timing and instant-on behavior matter more than raw clock frequency.
Được đề xuất
Peripheral Bus Interface Bridging
The EPM9560RI240-20C excels at bridging mismatched peripheral buses - such as ISA-to-PCI, microcontroller-to-DSP, or asynchronous-to-synchronous protocol conversion. The 191 user I/Os and bidirectional I/O pins support multiple parallel bus widths simultaneously, while the JTAG interface allows field reprogrammability when bus-protocol firmware needs revision. Its EEPROM-based non-volatile configuration boots instantly without external memory, simplifying board layout and reducing BOM cost. The 5 V tolerant I/Os interface cleanly with legacy 5 V peripherals.
Được đề xuất
Address Decoding and Chip Select Generation
For microprocessor systems with large memory maps, the EPM9560RI240-20C's 560 macrocells and 191 I/Os handle complex address decoding and chip-select generation across wide address buses. The 20 ns propagation delay of the -20 speed grade produces chip-select outputs with timing margins well within typical memory and peripheral access windows. Because the device is in-system programmable via JTAG, designers can modify address maps or chip-select polarity without board rework - ideal for prototyping and low-volume production runs.
Được đề xuất
High-Speed State Machine Controllers
The EPM9560RI240-20C implements complex Moore or Mealy state machines in deterministic, parallel hardware that runs up to 100 MHz internally. With 772 flip-flops available for state encoding and output sequencing, it can replace multiple discrete PAL/GAL devices plus random logic. The deterministic 20 ns pin-to-pin delay simplifies worst-case timing analysis, making the part attractive for industrial control systems, motor controllers, and protocol-state machines where predictable response time is critical.
Được đề xuất
Industrial Control and Instrumentation
In industrial control cabinets, the EPM9560RI240-20C delivers reliable glue logic and protocol conversion with the instant-on behavior required for deterministic system startup. Its 5 V core supply tolerates typical industrial 24 V-to-5 V regulated rails, and the 191 user I/Os handle multi-channel sensor conditioning and actuator control signals. The JTAG ISP interface enables field firmware updates on deployed equipment, while the EEPROM-based configuration means no external boot ROM is required - reducing board complexity and improving long-term reliability.
Được đề xuất
Legacy System Modernization
The EPM9560RI240-20C is widely used to modernize legacy 5 V systems by consolidating dozens of discrete 74F/74LS/74HC logic devices into a single programmable part. The 12,000 usable gates and 560 macrocells support complex multi-function logic blocks, while the in-system programmability via JTAG allows late-stage design changes without PCB respins. Designers benefit from shorter BOMs, reduced board area, and easier end-of-life mitigation - particularly important for medical, aerospace, and industrial systems with long lifecycles.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EPM9560RI240-20C — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EPM9560RI240-20 | EPM9560RI240-15C | EPM9560RI240-10 | EPM9480RC240-20 | EPM9480RC240-20C |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 240-pin RQFP | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same |
| Macrocells | 560 | 560 | 560 | 560 | 480 | 480 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 10,000 | 10,000 |
| Propagation Delay (tPD) | 20 ns (-20 grade) | 20 ns (-20) | 15 ns (-15 grade) | 10 ns (-10 grade) | 20 ns (-20) | 20 ns (-20) |
| User I/Os | 191 | 191 | 191 | 191 | 191 | 191 |
| Operating Temperature | 0 to +70 °C (commercial) | Industrial / wider | 0 to +70 °C (commercial) | Industrial / wider | Industrial / wider | 0 to +70 °C (commercial) |
Bảo phân biệt quan trọng
- Highest density in the MAX 9000 family (vsEPM9480RC240-20C)
- Commercial temperature grade at lower cost (vsEPM9560RI240-20)
- Standard -20 speed grade balances cost and timing margin (vsEPM9560RI240-10)
Ghi chú thiết kế
The EPM9560RI240-20C requires a stable 5 V VCCINT supply with adequate decoupling. Place one 0.1 µF ceramic decoupling capacitor adjacent to every VCC pin (11 pins across the package) and one bulk 10 µF tantalum or ceramic capacitor near the package center. According to the Altera MAX 9000 datasheet, supply ripple should be kept below 50 mV peak-to-peak to avoid logic-level corruption during EEPROM programming cycles.
Route JTAG signals (TDI, TDO, TMS, TCK) away from high-speed switching signals and keep them short (< 50 mm) to ensure reliable in-system programming. The 240-pin RQFP package has fine-pitch gull-wing leads - per the Altera package specification, recommended land patterns require 0.5 mm lead pitch with 0.3 mm stencil apertures for reflow. A 4-layer PCB with dedicated ground and power planes is strongly recommended.
Do not exceed the 5 V VCCINT maximum - the EPM9560RI240-20C is NOT a 3.3 V core device, only its I/O banks can be 3.3 V. Ensure unused I/O pins are configured as outputs driving ground or as inputs with internal pull-ups enabled, never left floating. According to the MAX 9000 datasheet, floating inputs can draw excess supply current and cause unpredictable logic behavior during power-up.
Thông tin tuân thủ
EPM9560RI240-20C is a legacy Altera (now Intel) MAX 9000 CPLD in NRD status. Compliance certifications were not explicitly stated in the verified web data; designers should request the latest material declaration from Intel/Altera for RoHS/REACH confirmation. Not qualified to AEC-Q100 (commercial temperature grade only).
