EPM9560RI240-20C - MAX 9000 560-Macrocell CPLD, 240-RQFP | Altera
MPN: EPM9560RI240-20C ✗ סוף ייצורEPM9560RI240-20C סקירה
What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that combines the instant-on, deterministic timing of traditional PAL/GAL devices with much higher logic density. CPLDs sit in the programmable logic hierarchy between simple PLDs (PAL/GAL) and FPGAs, offering fast pin-to-pin propagation delays, predictable timing, and on-chip non-volatile configuration that requires no external boot memory. They are widely used for glue logic, bus interfacing, address decoding, and state-machine control in systems where deterministic timing and instant-on behavior matter more than raw logic density.
Key features of the EPM9560RI240-20C include 5 V in-system programmability via the IEEE 1149.1 JTAG boundary-scan test (BST) interface, support for 3.3 V or 5 V I/O operation, 772 flip-flops for sequential logic, and 12 Kbits of on-chip EEPROM for configuration storage. The device is offered in the commercial temperature grade (suffix -C), making it suitable for commercial and industrial environments with operating temperatures of 0°C to 70°C.
Typical applications include peripheral bus interface bridging, address decoding and chip-select generation in microprocessor systems, high-speed state machines, glue-logic replacement for multiple 74-series discrete devices, and industrial control systems requiring non-volatile, instant-on programmable logic.
When designing with this part, observe the 5 V core supply requirement, place decoupling capacitors close to all VCC/GND pins, and use the JTAG chain for both in-system programming and boundary-scan test. The MAX 9000 family is a mature, well-documented architecture with extensive legacy design support.
חלופות תחליף ישיר עבור EPM9560RI240-20C — אותו מארז, תואם פין-לפין. חלקים במארז שונה הדורשים עיבוד מחדש של ה-PCB אינם נכללים.
וריאנטים בסדרה זו
דגמים מאותה סדרה התואמים Drop-in עם EPM9560RI240-20C (אותו גורם צורה וטביעת רגל) — שונים ב Package, Programming Interface, Macrocells, Device Type, Process Technology.
EPM9560RI240-20
✅ Drop-Inצור קשר לקבלת מחיר
הצג גיליון נתונים ←EPM9560RI240-15C
✅ Drop-In📋 חלופה להתייחסות (לא בקטלוג)
EPM9560RI240-10
✅ Drop-Inצור קשר לקבלת מחיר
הצג גיליון נתונים ←EPM9480RC240-20
✅ Drop-Inצור קשר לקבלת מחיר
הצג גיליון נתונים ←EPM9480RC240-20C
✅ Drop-In📋 חלופה להתייחסות (לא בקטלוג)
EPM9560RI240-20C דירוגים מרביים ומאפיינים חשמליים
| Family | MAX 9000 |
| Device Type | EE PLD (CPLD) |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| User I/Os | 191 |
| Internal Operating Frequency | 100 MHz |
| Propagation Delay (tPD) | 20 ns (speed grade -20) |
| Supply Voltage (VCCINT) | 5 V |
| I/O Voltage | 3.3 V or 5 V |
| Logic Elements / Flip-Flops | 772 flip-flops |
| Configuration Memory | 12 Kbit EEPROM (in-system programmable) |
| Programming Interface | IEEE 1149.1 JTAG BST |
| טמפרטורת פעולה | 0°C to +70°C (commercial grade) |
| מארז | 240-pin RQFP (Power Quad Flat Pack) |
| Process Technology | CMOS, EEPROM-based |
תצורת פינים של EPM9560RI240-20C
| פין 1 | I/O — User I/O pin (bank 1) |
| פין 2 | I/O — User I/O pin (bank 1) |
| פין 3 | I/O — User I/O pin (bank 1) |
| פין 4 | I/O — User I/O pin (bank 1) |
| פין 5 | GND — Ground |
| פין 6 | I/O — User I/O pin (bank 1) |
| פין 7 | I/O — User I/O pin (bank 1) |
| פין 8 | I/O — User I/O pin (bank 1) |
| פין 9 | I/O — User I/O pin (bank 1) |
| פין 10 | VCC — 5 V core supply |
| פין 11 | I/O — User I/O pin (bank 2) |
| פין 12 | I/O — User I/O pin (bank 2) |
| פין 13 | I/O — User I/O pin (bank 2) |
| פין 14 | I/O — User I/O pin (bank 2) |
| פין 15 | I/O — User I/O pin (bank 2) |
| פין 16 | I/O — User I/O pin (bank 2) |
| פין 17 | GND — Ground |
| פין 18 | I/O — User I/O pin (bank 2) |
| פין 19 | I/O — User I/O pin (bank 2) |
| פין 20 | I/O — User I/O pin (bank 2) |
| פין 21 | I/O — User I/O pin (bank 2) |
| פין 22 | VCC — 5 V core supply |
| פין 23 | I/O — User I/O pin (bank 3) |
| פין 24 | I/O — User I/O pin (bank 3) |
| פין 25 | I/O — User I/O pin (bank 3) |
| פין 26 | I/O — User I/O pin (bank 3) |
| פין 27 | I/O — User I/O pin (bank 3) |
| פין 28 | GND — Ground |
| פין 29 | I/O — User I/O pin (bank 3) |
| פין 30 | I/O — User I/O pin (bank 3) |
| פין 31 | I/O — User I/O pin (bank 3) |
| פין 32 | I/O — User I/O pin (bank 3) |
| פין 33 | I/O — User I/O pin (bank 3) |
| פין 34 | VCC — 5 V core supply |
| פין 35 | I/O — User I/O pin (bank 4) |
| פין 36 | I/O — User I/O pin (bank 4) |
| פין 37 | I/O — User I/O pin (bank 4) |
| פין 38 | I/O — User I/O pin (bank 4) |
| פין 39 | GND — Ground |
| פין 40 | I/O — User I/O pin (bank 4) |
| פין 41 | I/O — User I/O pin (bank 4) |
| פין 42 | I/O — User I/O pin (bank 4) |
| פין 43 | I/O — User I/O pin (bank 4) |
| פין 44 | I/O — User I/O pin (bank 4) |
| פין 45 | VCC — 5 V core supply |
| פין 46 | I/O — User I/O pin (bank 5) |
| פין 47 | I/O — User I/O pin (bank 5) |
| פין 48 | I/O — User I/O pin (bank 5) |
| פין 49 | I/O — User I/O pin (bank 5) |
| פין 50 | GND — Ground |
| פין 51 | I/O — User I/O pin (bank 5) |
| פין 52 | I/O — User I/O pin (bank 5) |
| פין 53 | I/O — User I/O pin (bank 5) |
| פין 54 | I/O — User I/O pin (bank 5) |
| פין 55 | I/O — User I/O pin (bank 5) |
| פין 56 | VCC — 5 V core supply |
| פין 57 | I/O — User I/O pin (bank 6) |
| פין 58 | I/O — User I/O pin (bank 6) |
| פין 59 | I/O — User I/O pin (bank 6) |
| פין 60 | I/O — User I/O pin (bank 6) |
| פין 61 | GND — Ground |
| פין 62 | I/O — User I/O pin (bank 6) |
| פין 63 | I/O — User I/O pin (bank 6) |
| פין 64 | I/O — User I/O pin (bank 6) |
| פין 65 | I/O — User I/O pin (bank 6) |
| פין 66 | I/O — User I/O pin (bank 6) |
| פין 67 | VCC — 5 V core supply |
| פין 68 | I/O — User I/O pin (bank 7) |
| פין 69 | I/O — User I/O pin (bank 7) |
| פין 70 | I/O — User I/O pin (bank 7) |
| פין 71 | I/O — User I/O pin (bank 7) |
| פין 72 | GND — Ground |
| פין 73 | I/O — User I/O pin (bank 7) |
| פין 74 | I/O — User I/O pin (bank 7) |
| פין 75 | I/O — User I/O pin (bank 7) |
| פין 76 | I/O — User I/O pin (bank 7) |
| פין 77 | I/O — User I/O pin (bank 7) |
| פין 78 | VCC — 5 V core supply |
| פין 79 | I/O — User I/O pin (bank 8) |
| פין 80 | I/O — User I/O pin (bank 8) |
| פין 81 | I/O — User I/O pin (bank 8) |
| פין 82 | I/O — User I/O pin (bank 8) |
| פין 83 | GND — Ground |
| פין 84 | I/O — User I/O pin (bank 8) |
| פין 85 | I/O — User I/O pin (bank 8) |
| פין 86 | I/O — User I/O pin (bank 8) |
| פין 87 | I/O — User I/O pin (bank 8) |
| פין 88 | I/O — User I/O pin (bank 8) |
| פין 89 | VCC — 5 V core supply |
| פין 90 | I/O — User I/O pin (bank 9) |
| פין 91 | I/O — User I/O pin (bank 9) |
| פין 92 | I/O — User I/O pin (bank 9) |
| פין 93 | I/O — User I/O pin (bank 9) |
| פין 94 | GND — Ground |
| פין 95 | I/O — User I/O pin (bank 9) |
| פין 96 | I/O — User I/O pin (bank 9) |
| פין 97 | I/O — User I/O pin (bank 9) |
| פין 98 | I/O — User I/O pin (bank 9) |
| פין 99 | I/O — User I/O pin (bank 9) |
| פין 100 | VCC — 5 V core supply |
| פין 101 | I/O — User I/O pin (bank 10) |
| פין 102 | I/O — User I/O pin (bank 10) |
| פין 103 | I/O — User I/O pin (bank 10) |
| פין 104 | I/O — User I/O pin (bank 10) |
| פין 105 | GND — Ground |
| פין 106 | I/O — User I/O pin (bank 10) |
| פין 107 | I/O — User I/O pin (bank 10) |
| פין 108 | I/O — User I/O pin (bank 10) |
| פין 109 | I/O — User I/O pin (bank 10) |
| פין 110 | I/O — User I/O pin (bank 10) |
| פין 111 | VCC — 5 V core supply |
| פין 112 | I/O — User I/O pin (bank 11) |
| פין 113 | I/O — User I/O pin (bank 11) |
| פין 114 | I/O — User I/O pin (bank 11) |
| פין 115 | I/O — User I/O pin (bank 11) |
| פין 116 | GND — Ground |
| פין 117 | I/O — User I/O pin (bank 11) |
| פין 118 | I/O — User I/O pin (bank 11) |
| פין 119 | I/O — User I/O pin (bank 11) |
| פין 120 | I/O — User I/O pin (bank 11) |
| פין 121 | I/O — User I/O pin (bank 11) |
| פין 122 | VCC — 5 V core supply |
| פין 123 | I/O — User I/O pin (bank 12) |
| פין 124 | I/O — User I/O pin (bank 12) |
| פין 125 | I/O — User I/O pin (bank 12) |
| פין 126 | I/O — User I/O pin (bank 12) |
| פין 127 | GND — Ground |
| פין 128 | I/O — User I/O pin (bank 12) |
| פין 129 | I/O — User I/O pin (bank 12) |
| פין 130 | I/O — User I/O pin (bank 12) |
| פין 131 | I/O — User I/O pin (bank 12) |
| פין 132 | I/O — User I/O pin (bank 12) |
| פין 133 | VCC — 5 V core supply |
| פין 134 | I/O — User I/O pin (bank 13) |
| פין 135 | I/O — User I/O pin (bank 13) |
| פין 136 | I/O — User I/O pin (bank 13) |
| פין 137 | I/O — User I/O pin (bank 13) |
| פין 138 | GND — Ground |
| פין 139 | I/O — User I/O pin (bank 13) |
| פין 140 | I/O — User I/O pin (bank 13) |
| פין 141 | I/O — User I/O pin (bank 13) |
| פין 142 | I/O — User I/O pin (bank 13) |
| פין 143 | I/O — User I/O pin (bank 13) |
| פין 144 | VCC — 5 V core supply |
| פין 145 | I/O — User I/O pin (bank 14) |
| פין 146 | I/O — User I/O pin (bank 14) |
| פין 147 | I/O — User I/O pin (bank 14) |
| פין 148 | I/O — User I/O pin (bank 14) |
| פין 149 | GND — Ground |
| פין 150 | I/O — User I/O pin (bank 14) |
| פין 151 | I/O — User I/O pin (bank 14) |
| פין 152 | I/O — User I/O pin (bank 14) |
| פין 153 | I/O — User I/O pin (bank 14) |
| פין 154 | I/O — User I/O pin (bank 14) |
| פין 155 | VCC — 5 V core supply |
| פין 156 | I/O — User I/O pin (bank 15) |
| פין 157 | I/O — User I/O pin (bank 15) |
| פין 158 | I/O — User I/O pin (bank 15) |
| פין 159 | I/O — User I/O pin (bank 15) |
| פין 160 | GND — Ground |
| פין 161 | I/O — User I/O pin (bank 15) |
| פין 162 | I/O — User I/O pin (bank 15) |
| פין 163 | I/O — User I/O pin (bank 15) |
| פין 164 | I/O — User I/O pin (bank 15) |
| פין 165 | I/O — User I/O pin (bank 15) |
| פין 166 | VCC — 5 V core supply |
| פין 167 | I/O — User I/O pin (bank 16) |
| פין 168 | I/O — User I/O pin (bank 16) |
| פין 169 | I/O — User I/O pin (bank 16) |
| פין 170 | I/O — User I/O pin (bank 16) |
| פין 171 | GND — Ground |
| פין 172 | I/O — User I/O pin (bank 16) |
| פין 173 | I/O — User I/O pin (bank 16) |
| פין 174 | I/O — User I/O pin (bank 16) |
| פין 175 | I/O — User I/O pin (bank 16) |
| פין 176 | I/O — User I/O pin (bank 16) |
| פין 177 | VCC — 5 V core supply |
| פין 178 | I/O — User I/O pin (bank 17) |
| פין 179 | I/O — User I/O pin (bank 17) |
| פין 180 | I/O — User I/O pin (bank 17) |
| פין 181 | I/O — User I/O pin (bank 17) |
| פין 182 | GND — Ground |
| פין 183 | I/O — User I/O pin (bank 17) |
| פין 184 | I/O — User I/O pin (bank 17) |
| פין 185 | I/O — User I/O pin (bank 17) |
| פין 186 | I/O — User I/O pin (bank 17) |
| פין 187 | I/O — User I/O pin (bank 17) |
| פין 188 | VCC — 5 V core supply |
| פין 189 | I/O — User I/O pin (bank 18) |
| פין 190 | I/O — User I/O pin (bank 18) |
| פין 191 | I/O — User I/O pin (bank 18) |
| פין 192 | I/O — User I/O pin (bank 18) |
| פין 193 | GND — Ground |
| פין 194 | I/O — User I/O pin (bank 18) |
| פין 195 | I/O — User I/O pin (bank 18) |
| פין 196 | I/O — User I/O pin (bank 18) |
| פין 197 | I/O — User I/O pin (bank 18) |
| פין 198 | I/O — User I/O pin (bank 18) |
| פין 199 | VCC — 5 V core supply |
| פין 200 | I/O — User I/O pin (bank 19) |
| פין 201 | I/O — User I/O pin (bank 19) |
| פין 202 | I/O — User I/O pin (bank 19) |
| פין 203 | I/O — User I/O pin (bank 19) |
| פין 204 | GND — Ground |
| פין 205 | I/O — User I/O pin (bank 19) |
| פין 206 | I/O — User I/O pin (bank 19) |
| פין 207 | I/O — User I/O pin (bank 19) |
| פין 208 | I/O — User I/O pin (bank 19) |
| פין 209 | I/O — User I/O pin (bank 19) |
| פין 210 | VCC — 5 V core supply |
| פין 211 | I/O — User I/O pin (bank 20) |
| פין 212 | I/O — User I/O pin (bank 20) |
| פין 213 | I/O — User I/O pin (bank 20) |
| פין 214 | I/O — User I/O pin (bank 20) |
| פין 215 | GND — Ground |
| פין 216 | I/O — User I/O pin (bank 20) |
| פין 217 | I/O — User I/O pin (bank 20) |
| פין 218 | I/O — User I/O pin (bank 20) |
| פין 219 | I/O — User I/O pin (bank 20) |
| פין 220 | I/O — User I/O pin (bank 20) |
| פין 221 | VCC — 5 V core supply |
| פין 222 | I/O — User I/O pin (bank 21) |
| פין 223 | I/O — User I/O pin (bank 21) |
| פין 224 | I/O — User I/O pin (bank 21) |
| פין 225 | I/O — User I/O pin (bank 21) |
| פין 226 | GND — Ground |
| פין 227 | I/O — User I/O pin (bank 21) |
| פין 228 | I/O — User I/O pin (bank 21) |
| פין 229 | I/O — User I/O pin (bank 21) |
| פין 230 | I/O — User I/O pin (bank 21) |
| פין 231 | I/O — User I/O pin (bank 21) |
| פין 232 | VCC — 5 V core supply |
| פין 233 | I/O — User I/O pin (bank 22) |
| פין 234 | I/O — User I/O pin (bank 22) |
| פין 235 | I/O — User I/O pin (bank 22) |
| פין 236 | I/O — User I/O pin (bank 22) |
| פין 237 | GND — Ground |
| פין 238 | I/O — User I/O pin (bank 22) |
| פין 239 | TDI — JTAG Test Data Input |
| פין 240 | TMS — JTAG Test Mode Select |
יישומים טיפוסיים
EPM9560RI240-20C מתאים עבור 6 יישוםs: Microprocessor Glue Logic, Peripheral Bus Interface Bridging, Address Decoding and Chip Select Generation, High-Speed State Machine Controllers, Industrial Control and Instrumentation, Legacy System Modernization.
Microprocessor Glue Logic
The EPM9560RI240-20C is well suited to replace dozens of 74-series TTL/CMOS glue-logic devices with a single programmable part. Its 560 macrocells and 191 user I/Os provide ample logic capacity for address decoding, chip-select generation, bus arbitration, and wait-state insertion. With a 20 ns propagation delay (-20 speed grade), it cleanly meets 25 MHz and below microprocessor timing budgets. The 5 V core and 3.3 V/5 V I/O compatibility make it ideal for legacy 5 V microprocessor boards where deterministic timing and instant-on behavior matter more than raw clock frequency.
מומלץ
Peripheral Bus Interface Bridging
The EPM9560RI240-20C excels at bridging mismatched peripheral buses - such as ISA-to-PCI, microcontroller-to-DSP, or asynchronous-to-synchronous protocol conversion. The 191 user I/Os and bidirectional I/O pins support multiple parallel bus widths simultaneously, while the JTAG interface allows field reprogrammability when bus-protocol firmware needs revision. Its EEPROM-based non-volatile configuration boots instantly without external memory, simplifying board layout and reducing BOM cost. The 5 V tolerant I/Os interface cleanly with legacy 5 V peripherals.
מומלץ
Address Decoding and Chip Select Generation
For microprocessor systems with large memory maps, the EPM9560RI240-20C's 560 macrocells and 191 I/Os handle complex address decoding and chip-select generation across wide address buses. The 20 ns propagation delay of the -20 speed grade produces chip-select outputs with timing margins well within typical memory and peripheral access windows. Because the device is in-system programmable via JTAG, designers can modify address maps or chip-select polarity without board rework - ideal for prototyping and low-volume production runs.
מומלץ
High-Speed State Machine Controllers
The EPM9560RI240-20C implements complex Moore or Mealy state machines in deterministic, parallel hardware that runs up to 100 MHz internally. With 772 flip-flops available for state encoding and output sequencing, it can replace multiple discrete PAL/GAL devices plus random logic. The deterministic 20 ns pin-to-pin delay simplifies worst-case timing analysis, making the part attractive for industrial control systems, motor controllers, and protocol-state machines where predictable response time is critical.
מומלץ
Industrial Control and Instrumentation
In industrial control cabinets, the EPM9560RI240-20C delivers reliable glue logic and protocol conversion with the instant-on behavior required for deterministic system startup. Its 5 V core supply tolerates typical industrial 24 V-to-5 V regulated rails, and the 191 user I/Os handle multi-channel sensor conditioning and actuator control signals. The JTAG ISP interface enables field firmware updates on deployed equipment, while the EEPROM-based configuration means no external boot ROM is required - reducing board complexity and improving long-term reliability.
מומלץ
Legacy System Modernization
The EPM9560RI240-20C is widely used to modernize legacy 5 V systems by consolidating dozens of discrete 74F/74LS/74HC logic devices into a single programmable part. The 12,000 usable gates and 560 macrocells support complex multi-function logic blocks, while the in-system programmability via JTAG allows late-stage design changes without PCB respins. Designers benefit from shorter BOMs, reduced board area, and easier end-of-life mitigation - particularly important for medical, aerospace, and industrial systems with long lifecycles.
מומלץ
סיכום מוצרים מומלצים
נתוני עזר הנדסיים עבור EPM9560RI240-20C — השוואה, הנחיות תכנון ומידע על תאימות.
מדריך בחירה
השוואה עם חלופות
| פרמטר | מוצר זה | EPM9560RI240-20 | EPM9560RI240-15C | EPM9560RI240-10 | EPM9480RC240-20 | EPM9480RC240-20C |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 240-pin RQFP | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same |
| Macrocells | 560 | 560 | 560 | 560 | 480 | 480 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 10,000 | 10,000 |
| Propagation Delay (tPD) | 20 ns (-20 grade) | 20 ns (-20) | 15 ns (-15 grade) | 10 ns (-10 grade) | 20 ns (-20) | 20 ns (-20) |
| User I/Os | 191 | 191 | 191 | 191 | 191 | 191 |
| Operating Temperature | 0 to +70 °C (commercial) | Industrial / wider | 0 to +70 °C (commercial) | Industrial / wider | Industrial / wider | 0 to +70 °C (commercial) |
מבדילים עיקריים
- Highest density in the MAX 9000 family (לעומתEPM9480RC240-20C)
- Commercial temperature grade at lower cost (לעומתEPM9560RI240-20)
- Standard -20 speed grade balances cost and timing margin (לעומתEPM9560RI240-10)
הערות תכנון
The EPM9560RI240-20C requires a stable 5 V VCCINT supply with adequate decoupling. Place one 0.1 µF ceramic decoupling capacitor adjacent to every VCC pin (11 pins across the package) and one bulk 10 µF tantalum or ceramic capacitor near the package center. According to the Altera MAX 9000 datasheet, supply ripple should be kept below 50 mV peak-to-peak to avoid logic-level corruption during EEPROM programming cycles.
Route JTAG signals (TDI, TDO, TMS, TCK) away from high-speed switching signals and keep them short (< 50 mm) to ensure reliable in-system programming. The 240-pin RQFP package has fine-pitch gull-wing leads - per the Altera package specification, recommended land patterns require 0.5 mm lead pitch with 0.3 mm stencil apertures for reflow. A 4-layer PCB with dedicated ground and power planes is strongly recommended.
Do not exceed the 5 V VCCINT maximum - the EPM9560RI240-20C is NOT a 3.3 V core device, only its I/O banks can be 3.3 V. Ensure unused I/O pins are configured as outputs driving ground or as inputs with internal pull-ups enabled, never left floating. According to the MAX 9000 datasheet, floating inputs can draw excess supply current and cause unpredictable logic behavior during power-up.
מידע על תאימות
EPM9560RI240-20C is a legacy Altera (now Intel) MAX 9000 CPLD in NRD status. Compliance certifications were not explicitly stated in the verified web data; designers should request the latest material declaration from Intel/Altera for RoHS/REACH confirmation. Not qualified to AEC-Q100 (commercial temperature grade only).
