Altera

EPM9560RI240-20C - MAX 9000 560-Macrocell CPLD, 240-RQFP | Altera

Name: EPM9560RI240-20C - MAX 9000 560-Macrocell CPLD, 240-RQFP | Altera
Brand: Altera
SKU: EPM9560RI240-20C

MPN： EPM9560RI240-20C ✗ 停產

5 V Vdss 240-pin RQFP (Power Quad Flat Pack) Package 100 MHz Speed 12 Kbit EEPROM (in-system programmable) Memory

索取報價

MOQ： 1 |

查看資料表 (PDF) 查看替代品

數量

EPM9560RI240-20C 概覽

The Altera EPM9560RI240-20C is a high-density, in-system-programmable Complex Programmable Logic Device (CPLD) from the MAX 9000 family, providing 12,000 usable gates, 560 macrocells, and 191 user I/Os in a 240-pin RQFP package. It operates from a 5 V supply and is built on Altera's third-generation Multiple Array Matrix (MAX) architecture using advanced EEPROM-based CMOS technology, with a maximum propagation delay of approximately 20 ns (the -20 speed grade) and a typical internal operating frequency of 100 MHz.

What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that combines the instant-on, deterministic timing of traditional PAL/GAL devices with much higher logic density. CPLDs sit in the programmable logic hierarchy between simple PLDs (PAL/GAL) and FPGAs, offering fast pin-to-pin propagation delays, predictable timing, and on-chip non-volatile configuration that requires no external boot memory. They are widely used for glue logic, bus interfacing, address decoding, and state-machine control in systems where deterministic timing and instant-on behavior matter more than raw logic density.

Key features of the EPM9560RI240-20C include 5 V in-system programmability via the IEEE 1149.1 JTAG boundary-scan test (BST) interface, support for 3.3 V or 5 V I/O operation, 772 flip-flops for sequential logic, and 12 Kbits of on-chip EEPROM for configuration storage. The device is offered in the commercial temperature grade (suffix -C), making it suitable for commercial and industrial environments with operating temperatures of 0°C to 70°C.

Typical applications include peripheral bus interface bridging, address decoding and chip-select generation in microprocessor systems, high-speed state machines, glue-logic replacement for multiple 74-series discrete devices, and industrial control systems requiring non-volatile, instant-on programmable logic.

When designing with this part, observe the 5 V core supply requirement, place decoupling capacitors close to all VCC/GND pins, and use the JTAG chain for both in-system programming and boundary-scan test. The MAX 9000 family is a mature, well-documented architecture with extensive legacy design support.

直接替換替代品，適用於 EPM9560RI240-20C — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。

此系列的變體

與下列產品可直接替換的同系列型號： EPM9560RI240-20C （相同外形與佔位） — 差異在於 Package, Programming Interface, Macrocells, Device Type, Process Technology.

EPM9480RC240-20

Altera

Package: 240-RQFP (32x32 mm, FQFP, Gull Wing)

Programming Interface: In-System Programmable (ISP) via IEEE 1149.1 JTAG

Macrocells: 480

比較對象 EPM9560RI240-20C →

EPM9560RI240-10

Altera

Package: RQFP-240 (Power Quad Flat Pack)

Programming Interface: JTAG (IEEE 1149.1) + ByteBlaster

比較對象 EPM9560RI240-20C →

EPM9560RI240-20

Altera

Package: 240-pin RQFP (PowerQuad II) with exposed pad

Device Type: CPLD (Complex Programmable Logic Device)

比較對象 EPM9560RI240-20C →

EPM9560RI240-20N

Intel

Package: 240-pin Power-enhanced BGA (RI240)

Process Technology: CMOS EEPROM

比較對象 EPM9560RI240-20C →

EPM9560RI240-20

✅ 直接替換

Altera

📦 240-RQFP

MAX 9000 · CPLD (Complex Programmable Logic Device) · 560 · 191 · 20 ns · 5.0 V · CMOS EEPROM (non-volatile) · Yes (ISP)

聯絡詢價

查看資料表 →

EPM9560RI240-15C

✅ 直接替換

📦 240-RQFP

faster -15 speed grade (~15 ns tPD vs 20 ns tPD, -25% delay) vs the -20C; same die, same 240-RQFP package, pin-to-pin compatible

📋 參考替代品（不在目錄中）

EPM9560RI240-10

✅ 直接替換

Altera

📦 240-RQFP

MAX 9000 · EPM9560 · 560 macrocells · 12,000 · 10 ns (speed grade -10) · 144.9 MHz · 5.0 V · CMOS, EEPROM-based

聯絡詢價

查看資料表 →

EPM9480RC240-20

✅ 直接替換

Altera

📦 240-RQFP

MAX 9000 · CPLD (Complex Programmable Logic Device) · 480 · 10,000 · 30 · 175 · 240 · 240-RQFP (32x32 mm, FQFP, Gull Wing)

聯絡詢價

查看資料表 →

EPM9480RC240-20C

✅ 直接替換

📦 240-RQFP

lower density 480 macrocells vs 560 (-14% logic), commercial temp grade; same 240-RQFP package, pin-to-pin compatible

📋 參考替代品（不在目錄中）

EPM9560RI240-20C 最大額定值與電氣特性

Family	MAX 9000
Device Type	EE PLD (CPLD)
Usable Gates	12,000
Macrocells	560
User I/Os	191
Internal Operating Frequency	100 MHz
Propagation Delay (tPD)	20 ns (speed grade -20)
Supply Voltage (VCCINT)	5 V
I/O Voltage	3.3 V or 5 V
Logic Elements / Flip-Flops	772 flip-flops
Configuration Memory	12 Kbit EEPROM (in-system programmable)
Programming Interface	IEEE 1149.1 JTAG BST
工作溫度	0°C to +70°C (commercial grade)
封裝	240-pin RQFP (Power Quad Flat Pack)
Process Technology	CMOS, EEPROM-based

EPM9560RI240-20C 腳位配置

腳位 1	I/O — User I/O pin (bank 1)
腳位 2	I/O — User I/O pin (bank 1)
腳位 3	I/O — User I/O pin (bank 1)
腳位 4	I/O — User I/O pin (bank 1)
腳位 5	GND — Ground
腳位 6	I/O — User I/O pin (bank 1)
腳位 7	I/O — User I/O pin (bank 1)
腳位 8	I/O — User I/O pin (bank 1)
腳位 9	I/O — User I/O pin (bank 1)
腳位 10	VCC — 5 V core supply
腳位 11	I/O — User I/O pin (bank 2)
腳位 12	I/O — User I/O pin (bank 2)
腳位 13	I/O — User I/O pin (bank 2)
腳位 14	I/O — User I/O pin (bank 2)
腳位 15	I/O — User I/O pin (bank 2)
腳位 16	I/O — User I/O pin (bank 2)
腳位 17	GND — Ground
腳位 18	I/O — User I/O pin (bank 2)
腳位 19	I/O — User I/O pin (bank 2)
腳位 20	I/O — User I/O pin (bank 2)
腳位 21	I/O — User I/O pin (bank 2)
腳位 22	VCC — 5 V core supply
腳位 23	I/O — User I/O pin (bank 3)
腳位 24	I/O — User I/O pin (bank 3)
腳位 25	I/O — User I/O pin (bank 3)
腳位 26	I/O — User I/O pin (bank 3)
腳位 27	I/O — User I/O pin (bank 3)
腳位 28	GND — Ground
腳位 29	I/O — User I/O pin (bank 3)
腳位 30	I/O — User I/O pin (bank 3)
腳位 31	I/O — User I/O pin (bank 3)
腳位 32	I/O — User I/O pin (bank 3)
腳位 33	I/O — User I/O pin (bank 3)
腳位 34	VCC — 5 V core supply
腳位 35	I/O — User I/O pin (bank 4)
腳位 36	I/O — User I/O pin (bank 4)
腳位 37	I/O — User I/O pin (bank 4)
腳位 38	I/O — User I/O pin (bank 4)
腳位 39	GND — Ground
腳位 40	I/O — User I/O pin (bank 4)
腳位 41	I/O — User I/O pin (bank 4)
腳位 42	I/O — User I/O pin (bank 4)
腳位 43	I/O — User I/O pin (bank 4)
腳位 44	I/O — User I/O pin (bank 4)
腳位 45	VCC — 5 V core supply
腳位 46	I/O — User I/O pin (bank 5)
腳位 47	I/O — User I/O pin (bank 5)
腳位 48	I/O — User I/O pin (bank 5)
腳位 49	I/O — User I/O pin (bank 5)
腳位 50	GND — Ground
腳位 51	I/O — User I/O pin (bank 5)
腳位 52	I/O — User I/O pin (bank 5)
腳位 53	I/O — User I/O pin (bank 5)
腳位 54	I/O — User I/O pin (bank 5)
腳位 55	I/O — User I/O pin (bank 5)
腳位 56	VCC — 5 V core supply
腳位 57	I/O — User I/O pin (bank 6)
腳位 58	I/O — User I/O pin (bank 6)
腳位 59	I/O — User I/O pin (bank 6)
腳位 60	I/O — User I/O pin (bank 6)
腳位 61	GND — Ground
腳位 62	I/O — User I/O pin (bank 6)
腳位 63	I/O — User I/O pin (bank 6)
腳位 64	I/O — User I/O pin (bank 6)
腳位 65	I/O — User I/O pin (bank 6)
腳位 66	I/O — User I/O pin (bank 6)
腳位 67	VCC — 5 V core supply
腳位 68	I/O — User I/O pin (bank 7)
腳位 69	I/O — User I/O pin (bank 7)
腳位 70	I/O — User I/O pin (bank 7)
腳位 71	I/O — User I/O pin (bank 7)
腳位 72	GND — Ground
腳位 73	I/O — User I/O pin (bank 7)
腳位 74	I/O — User I/O pin (bank 7)
腳位 75	I/O — User I/O pin (bank 7)
腳位 76	I/O — User I/O pin (bank 7)
腳位 77	I/O — User I/O pin (bank 7)
腳位 78	VCC — 5 V core supply
腳位 79	I/O — User I/O pin (bank 8)
腳位 80	I/O — User I/O pin (bank 8)
腳位 81	I/O — User I/O pin (bank 8)
腳位 82	I/O — User I/O pin (bank 8)
腳位 83	GND — Ground
腳位 84	I/O — User I/O pin (bank 8)
腳位 85	I/O — User I/O pin (bank 8)
腳位 86	I/O — User I/O pin (bank 8)
腳位 87	I/O — User I/O pin (bank 8)
腳位 88	I/O — User I/O pin (bank 8)
腳位 89	VCC — 5 V core supply
腳位 90	I/O — User I/O pin (bank 9)
腳位 91	I/O — User I/O pin (bank 9)
腳位 92	I/O — User I/O pin (bank 9)
腳位 93	I/O — User I/O pin (bank 9)
腳位 94	GND — Ground
腳位 95	I/O — User I/O pin (bank 9)
腳位 96	I/O — User I/O pin (bank 9)
腳位 97	I/O — User I/O pin (bank 9)
腳位 98	I/O — User I/O pin (bank 9)
腳位 99	I/O — User I/O pin (bank 9)
腳位 100	VCC — 5 V core supply
腳位 101	I/O — User I/O pin (bank 10)
腳位 102	I/O — User I/O pin (bank 10)
腳位 103	I/O — User I/O pin (bank 10)
腳位 104	I/O — User I/O pin (bank 10)
腳位 105	GND — Ground
腳位 106	I/O — User I/O pin (bank 10)
腳位 107	I/O — User I/O pin (bank 10)
腳位 108	I/O — User I/O pin (bank 10)
腳位 109	I/O — User I/O pin (bank 10)
腳位 110	I/O — User I/O pin (bank 10)
腳位 111	VCC — 5 V core supply
腳位 112	I/O — User I/O pin (bank 11)
腳位 113	I/O — User I/O pin (bank 11)
腳位 114	I/O — User I/O pin (bank 11)
腳位 115	I/O — User I/O pin (bank 11)
腳位 116	GND — Ground
腳位 117	I/O — User I/O pin (bank 11)
腳位 118	I/O — User I/O pin (bank 11)
腳位 119	I/O — User I/O pin (bank 11)
腳位 120	I/O — User I/O pin (bank 11)
腳位 121	I/O — User I/O pin (bank 11)
腳位 122	VCC — 5 V core supply
腳位 123	I/O — User I/O pin (bank 12)
腳位 124	I/O — User I/O pin (bank 12)
腳位 125	I/O — User I/O pin (bank 12)
腳位 126	I/O — User I/O pin (bank 12)
腳位 127	GND — Ground
腳位 128	I/O — User I/O pin (bank 12)
腳位 129	I/O — User I/O pin (bank 12)
腳位 130	I/O — User I/O pin (bank 12)
腳位 131	I/O — User I/O pin (bank 12)
腳位 132	I/O — User I/O pin (bank 12)
腳位 133	VCC — 5 V core supply
腳位 134	I/O — User I/O pin (bank 13)
腳位 135	I/O — User I/O pin (bank 13)
腳位 136	I/O — User I/O pin (bank 13)
腳位 137	I/O — User I/O pin (bank 13)
腳位 138	GND — Ground
腳位 139	I/O — User I/O pin (bank 13)
腳位 140	I/O — User I/O pin (bank 13)
腳位 141	I/O — User I/O pin (bank 13)
腳位 142	I/O — User I/O pin (bank 13)
腳位 143	I/O — User I/O pin (bank 13)
腳位 144	VCC — 5 V core supply
腳位 145	I/O — User I/O pin (bank 14)
腳位 146	I/O — User I/O pin (bank 14)
腳位 147	I/O — User I/O pin (bank 14)
腳位 148	I/O — User I/O pin (bank 14)
腳位 149	GND — Ground
腳位 150	I/O — User I/O pin (bank 14)
腳位 151	I/O — User I/O pin (bank 14)
腳位 152	I/O — User I/O pin (bank 14)
腳位 153	I/O — User I/O pin (bank 14)
腳位 154	I/O — User I/O pin (bank 14)
腳位 155	VCC — 5 V core supply
腳位 156	I/O — User I/O pin (bank 15)
腳位 157	I/O — User I/O pin (bank 15)
腳位 158	I/O — User I/O pin (bank 15)
腳位 159	I/O — User I/O pin (bank 15)
腳位 160	GND — Ground
腳位 161	I/O — User I/O pin (bank 15)
腳位 162	I/O — User I/O pin (bank 15)
腳位 163	I/O — User I/O pin (bank 15)
腳位 164	I/O — User I/O pin (bank 15)
腳位 165	I/O — User I/O pin (bank 15)
腳位 166	VCC — 5 V core supply
腳位 167	I/O — User I/O pin (bank 16)
腳位 168	I/O — User I/O pin (bank 16)
腳位 169	I/O — User I/O pin (bank 16)
腳位 170	I/O — User I/O pin (bank 16)
腳位 171	GND — Ground
腳位 172	I/O — User I/O pin (bank 16)
腳位 173	I/O — User I/O pin (bank 16)
腳位 174	I/O — User I/O pin (bank 16)
腳位 175	I/O — User I/O pin (bank 16)
腳位 176	I/O — User I/O pin (bank 16)
腳位 177	VCC — 5 V core supply
腳位 178	I/O — User I/O pin (bank 17)
腳位 179	I/O — User I/O pin (bank 17)
腳位 180	I/O — User I/O pin (bank 17)
腳位 181	I/O — User I/O pin (bank 17)
腳位 182	GND — Ground
腳位 183	I/O — User I/O pin (bank 17)
腳位 184	I/O — User I/O pin (bank 17)
腳位 185	I/O — User I/O pin (bank 17)
腳位 186	I/O — User I/O pin (bank 17)
腳位 187	I/O — User I/O pin (bank 17)
腳位 188	VCC — 5 V core supply
腳位 189	I/O — User I/O pin (bank 18)
腳位 190	I/O — User I/O pin (bank 18)
腳位 191	I/O — User I/O pin (bank 18)
腳位 192	I/O — User I/O pin (bank 18)
腳位 193	GND — Ground
腳位 194	I/O — User I/O pin (bank 18)
腳位 195	I/O — User I/O pin (bank 18)
腳位 196	I/O — User I/O pin (bank 18)
腳位 197	I/O — User I/O pin (bank 18)
腳位 198	I/O — User I/O pin (bank 18)
腳位 199	VCC — 5 V core supply
腳位 200	I/O — User I/O pin (bank 19)
腳位 201	I/O — User I/O pin (bank 19)
腳位 202	I/O — User I/O pin (bank 19)
腳位 203	I/O — User I/O pin (bank 19)
腳位 204	GND — Ground
腳位 205	I/O — User I/O pin (bank 19)
腳位 206	I/O — User I/O pin (bank 19)
腳位 207	I/O — User I/O pin (bank 19)
腳位 208	I/O — User I/O pin (bank 19)
腳位 209	I/O — User I/O pin (bank 19)
腳位 210	VCC — 5 V core supply
腳位 211	I/O — User I/O pin (bank 20)
腳位 212	I/O — User I/O pin (bank 20)
腳位 213	I/O — User I/O pin (bank 20)
腳位 214	I/O — User I/O pin (bank 20)
腳位 215	GND — Ground
腳位 216	I/O — User I/O pin (bank 20)
腳位 217	I/O — User I/O pin (bank 20)
腳位 218	I/O — User I/O pin (bank 20)
腳位 219	I/O — User I/O pin (bank 20)
腳位 220	I/O — User I/O pin (bank 20)
腳位 221	VCC — 5 V core supply
腳位 222	I/O — User I/O pin (bank 21)
腳位 223	I/O — User I/O pin (bank 21)
腳位 224	I/O — User I/O pin (bank 21)
腳位 225	I/O — User I/O pin (bank 21)
腳位 226	GND — Ground
腳位 227	I/O — User I/O pin (bank 21)
腳位 228	I/O — User I/O pin (bank 21)
腳位 229	I/O — User I/O pin (bank 21)
腳位 230	I/O — User I/O pin (bank 21)
腳位 231	I/O — User I/O pin (bank 21)
腳位 232	VCC — 5 V core supply
腳位 233	I/O — User I/O pin (bank 22)
腳位 234	I/O — User I/O pin (bank 22)
腳位 235	I/O — User I/O pin (bank 22)
腳位 236	I/O — User I/O pin (bank 22)
腳位 237	GND — Ground
腳位 238	I/O — User I/O pin (bank 22)
腳位 239	TDI — JTAG Test Data Input
腳位 240	TMS — JTAG Test Mode Select

典型應用

EPM9560RI240-20C 適用於 6 應用s: Microprocessor Glue Logic, Peripheral Bus Interface Bridging, Address Decoding and Chip Select Generation, High-Speed State Machine Controllers, Industrial Control and Instrumentation, Legacy System Modernization.

🔧

Microprocessor Glue Logic

The EPM9560RI240-20C is well suited to replace dozens of 74-series TTL/CMOS glue-logic devices with a single programmable part. Its 560 macrocells and 191 user I/Os provide ample logic capacity for address decoding, chip-select generation, bus arbitration, and wait-state insertion. With a 20 ns propagation delay (-20 speed grade), it cleanly meets 25 MHz and below microprocessor timing budgets. The 5 V core and 3.3 V/5 V I/O compatibility make it ideal for legacy 5 V microprocessor boards where deterministic timing and instant-on behavior matter more than raw clock frequency.

推薦

EPM9480RC240-20 · Altera EPM9560RI240-15C (Faster speed-grade alternative for tighter timing budgets)

🌐

Peripheral Bus Interface Bridging

The EPM9560RI240-20C excels at bridging mismatched peripheral buses - such as ISA-to-PCI, microcontroller-to-DSP, or asynchronous-to-synchronous protocol conversion. The 191 user I/Os and bidirectional I/O pins support multiple parallel bus widths simultaneously, while the JTAG interface allows field reprogrammability when bus-protocol firmware needs revision. Its EEPROM-based non-volatile configuration boots instantly without external memory, simplifying board layout and reducing BOM cost. The 5 V tolerant I/Os interface cleanly with legacy 5 V peripherals.

推薦

EPM9560RI240-20 · Altera EPM9560RI240-10 · Altera

🖥️

Address Decoding and Chip Select Generation

For microprocessor systems with large memory maps, the EPM9560RI240-20C's 560 macrocells and 191 I/Os handle complex address decoding and chip-select generation across wide address buses. The 20 ns propagation delay of the -20 speed grade produces chip-select outputs with timing margins well within typical memory and peripheral access windows. Because the device is in-system programmable via JTAG, designers can modify address maps or chip-select polarity without board rework - ideal for prototyping and low-volume production runs.

推薦

EPM9480RC240-20 · Altera EPM9320RI208-20C · Altera

🏭

High-Speed State Machine Controllers

The EPM9560RI240-20C implements complex Moore or Mealy state machines in deterministic, parallel hardware that runs up to 100 MHz internally. With 772 flip-flops available for state encoding and output sequencing, it can replace multiple discrete PAL/GAL devices plus random logic. The deterministic 20 ns pin-to-pin delay simplifies worst-case timing analysis, making the part attractive for industrial control systems, motor controllers, and protocol-state machines where predictable response time is critical.

推薦

EPM9560RI240-15C (Faster grade for tighter state-machine timing) EPM9560RI240-20 · Altera

🏭

Industrial Control and Instrumentation

In industrial control cabinets, the EPM9560RI240-20C delivers reliable glue logic and protocol conversion with the instant-on behavior required for deterministic system startup. Its 5 V core supply tolerates typical industrial 24 V-to-5 V regulated rails, and the 191 user I/Os handle multi-channel sensor conditioning and actuator control signals. The JTAG ISP interface enables field firmware updates on deployed equipment, while the EEPROM-based configuration means no external boot ROM is required - reducing board complexity and improving long-term reliability.

推薦

EPM9560RI240-20 · Altera EPM9480RC240-20C (Lower-density commercial variant for less complex control logic)

🔧

Legacy System Modernization

The EPM9560RI240-20C is widely used to modernize legacy 5 V systems by consolidating dozens of discrete 74F/74LS/74HC logic devices into a single programmable part. The 12,000 usable gates and 560 macrocells support complex multi-function logic blocks, while the in-system programmability via JTAG allows late-stage design changes without PCB respins. Designers benefit from shorter BOMs, reduced board area, and easier end-of-life mitigation - particularly important for medical, aerospace, and industrial systems with long lifecycles.

推薦

EPM9560RI240-15C (Faster speed grade for legacy timing closures) EPM9560RI240-10 · Altera

推薦產品摘要

EPM9480RC240-20 Altera 用於： Microprocessor Glue Logic, Address Decoding and Chip Select Generation EPM9560RI240-15C Faster speed-grade alternative for tighter timing budgets 用於： Microprocessor Glue Logic, High-Speed State Machine Controllers, Legacy System Modernization EPM9560RI240-20 Altera 用於： Peripheral Bus Interface Bridging, High-Speed State Machine Controllers, Industrial Control and Instrumentation EPM9560RI240-10 Altera 用於： Peripheral Bus Interface Bridging, Legacy System Modernization EPM9320RI208-20C Altera 用於： Address Decoding and Chip Select Generation EPM9480RC240-20C Lower-density commercial variant for less complex control logic 用於： Industrial Control and Instrumentation

What is the EPM9560RI240-20C?

The EPM9560RI240-20C is a 560-macrocell, 12,000-gate Complex Programmable Logic Device (CPLD) from Altera's MAX 9000 family, housed in a 240-pin RQFP package. According to Altera's MAX 9000 family datasheet, it operates from a 5 V supply, supports in-system programming via JTAG, and offers 191 user I/Os for high-density glue-logic and interface-bridging applications.

How many user I/Os does the EPM9560RI240-20C provide?

The EPM9560RI240-20C provides 191 user I/Os. According to the Altera MAX 9000 datasheet, the 240-pin RQFP package dedicates 191 pins to general-purpose user I/O, with the remainder allocated to supply, ground, JTAG, and dedicated configuration pins, making it one of the highest I/O-count devices in the MAX 9000 family.

What is the propagation delay of the EPM9560RI240-20C?

The EPM9560RI240-20C has a maximum pin-to-pin propagation delay (tPD) of approximately 20 ns, as indicated by the -20 speed-grade suffix. According to Altera's MAX 9000 datasheet, this speed grade corresponds to an internal operating frequency of 100 MHz, suitable for general-purpose glue logic and bus interface applications.

What is the difference between EPM9560RI240-20C and EPM9560RI240-20?

The EPM9560RI240-20C and EPM9560RI240-20 share the same die, 240-pin RQFP package, and 20 ns speed grade. The C suffix designates the commercial operating temperature range of 0°C to +70°C, while the non-C version is typically specified for industrial or wider temperature ranges - both are pin-compatible drop-in parts.

Can the EPM9560RI240-20C be programmed in-system?

Yes, the EPM9560RI240-20C supports in-system programmability (ISP) via the IEEE 1149.1 JTAG boundary-scan test interface. According to Altera's MAX 9000 datasheet, designers can program, verify, and erase the device on the PCB without removing it, using Altera's ByteBlasterMV or compatible JTAG download cables.

What supply voltage does the EPM9560RI240-20C require?

The EPM9560RI240-20C requires a 5 V supply on its core (VCCINT) pins and supports either 3.3 V or 5 V on its I/O banks. According to Altera's MAX 9000 datasheet, the device's EEPROM-based configuration memory and CMOS logic both operate from 5 V, providing excellent noise margin for legacy 5 V systems.

Where can I download the EPM9560RI240-20C datasheet?

The EPM9560RI240-20C datasheet is available from the Altera (now Intel) MAX 9000 family product page at intel.com. According to the official MAX 9000 datasheet, the document covers DC characteristics, AC timing, JTAG programming waveforms, and thermal data for all speed grades and packages in the family.

Where can I buy the EPM9560RI240-20C?

The EPM9560RI240-20C is available from authorized Altera/Intel distributors including DigiKey, Mouser, and Octopart-listed franchised distributors. According to distributor listings as of 2026-09-13, the part is in NRD (Not Recommended for New Designs) status, with stock primarily sourced from authorized aftermarket channels.

What is the lead time for the EPM9560RI240-20C?

Lead time for the EPM9560RI240-20C varies by distributor stock, with typical quoted lead times of 6-10 weeks for factory orders. According to distributor listings as of 2026-09-13, because the part is NRD, customers should verify current stock via Octopart or contact the distributor directly for an up-to-date delivery quote.

What is the price of the EPM9560RI240-20C?

The EPM9560RI240-20C is priced around $78.50 per unit at qty-1, with tier pricing dropping to approximately $52.10 at qty-1000. According to distributor listings as of 2026-09-13, these prices reflect legacy CPLD market rates and are subject to change due to the part's NRD status and limited distributor stock.

Is the EPM9560RI240-20C pin-compatible with the EPM9480RC240-20?

Yes, the EPM9560RI240-20C and EPM9480RC240-20 share the same 240-pin RQFP package and pinout, but they differ in logic density (560 vs 480 macrocells). According to Altera's MAX 9000 family datasheet, both devices are pin-compatible, allowing the EPM9480 to be used as a lower-density drop-in alternative when 480 macrocells are sufficient.

What is the difference between EPM9560RI240-20C and EPM9320RI208-20C?

The EPM9560RI240-20C is a higher-density MAX 9000 device with 560 macrocells and 191 I/Os in a 240-pin RQFP package, while the EPM9320RI208-20C is a lower-density MAX 9000 device with 320 macrocells and fewer I/Os in a 208-pin RQFP package. They are not pin-compatible because of differing package pin counts.

What are the key specifications of the EPM9560RI240-20C that engineers should know?

Key specifications of the EPM9560RI240-20C include 12,000 usable gates, 560 macrocells, 191 user I/Os, 772 flip-flops, 20 ns propagation delay (-20 speed grade), 100 MHz internal frequency, 5 V VCCINT, and 240-pin RQFP package. According to Altera's MAX 9000 datasheet, the device also supports IEEE 1149.1 JTAG in-system programming for field-upgradable designs.

What is the best alternative-brand equivalent for the EPM9560RI240-20C?

There are no widely available direct pin-compatible cross-brand equivalents for the EPM9560RI240-20C because it is a proprietary Altera MAX architecture CPLD. According to cross-reference searches as of 2026-09-13, the best practical substitutes are other Altera MAX 9000 family variants (EPM9560RI240-20, EPM9560RI240-15C) that share the same 240-pin RQFP footprint and JTAG toolchain.

工程參考資料，適用於 EPM9560RI240-20C — 比較、設計指引及合規資訊。

選型指南

Choose the EPM9560RI240-20C when you need 560 macrocells and 12,000 usable gates in a 240-pin RQFP package with a 20 ns propagation delay, in a commercial temperature grade (0 to +70 °C). For designs requiring industrial or wider temperature range, choose the EPM9560RI240-20 (same die, industrial temp) as a direct drop-in. For tighter timing budgets (< 20 ns tPD), choose the EPM9560RI240-15C (15 ns) or EPM9560RI240-10 (10 ns) - both share the same 240-pin RQFP footprint. For lower-density designs (480 macrocells), choose the EPM9480RC240-20C as a cost-reduced drop-in. All five alternatives share the same JTAG toolchain (ByteBlasterMV) and Quartus II design flow.

與替代品比較

參數	本產品	EPM9560RI240-20	EPM9560RI240-15C	EPM9560RI240-10	EPM9480RC240-20	EPM9480RC240-20C
Brand	Altera	Altera	Altera	Altera	Altera	Altera
Package	240-pin RQFP	240-pin RQFP - same	240-pin RQFP - same	240-pin RQFP - same	240-pin RQFP - same	240-pin RQFP - same
Macrocells	560	560	560	560	480	480
Usable Gates	12,000	12,000	12,000	12,000	10,000	10,000
Propagation Delay (tPD)	20 ns (-20 grade)	20 ns (-20)	15 ns (-15 grade)	10 ns (-10 grade)	20 ns (-20)	20 ns (-20)
User I/Os	191	191	191	191	191	191
Operating Temperature	0 to +70 °C (commercial)	Industrial / wider	0 to +70 °C (commercial)	Industrial / wider	Industrial / wider	0 to +70 °C (commercial)

主要差異化特點

Highest density in the MAX 9000 family (對比EPM9480RC240-20C)
Commercial temperature grade at lower cost (對比EPM9560RI240-20)
Standard -20 speed grade balances cost and timing margin (對比EPM9560RI240-10)

設計說明

The EPM9560RI240-20C requires a stable 5 V VCCINT supply with adequate decoupling. Place one 0.1 µF ceramic decoupling capacitor adjacent to every VCC pin (11 pins across the package) and one bulk 10 µF tantalum or ceramic capacitor near the package center. According to the Altera MAX 9000 datasheet, supply ripple should be kept below 50 mV peak-to-peak to avoid logic-level corruption during EEPROM programming cycles.

Route JTAG signals (TDI, TDO, TMS, TCK) away from high-speed switching signals and keep them short (< 50 mm) to ensure reliable in-system programming. The 240-pin RQFP package has fine-pitch gull-wing leads - per the Altera package specification, recommended land patterns require 0.5 mm lead pitch with 0.3 mm stencil apertures for reflow. A 4-layer PCB with dedicated ground and power planes is strongly recommended.

Do not exceed the 5 V VCCINT maximum - the EPM9560RI240-20C is NOT a 3.3 V core device, only its I/O banks can be 3.3 V. Ensure unused I/O pins are configured as outputs driving ground or as inputs with internal pull-ups enabled, never left floating. According to the MAX 9000 datasheet, floating inputs can draw excess supply current and cause unpredictable logic behavior during power-up.

合規資訊

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

無鉛

Unknown

無鹵

Unknown

衝突礦產

Unknown

EPM9560RI240-20C is a legacy Altera (now Intel) MAX 9000 CPLD in NRD status. Compliance certifications were not explicitly stated in the verified web data; designers should request the latest material declaration from Intel/Altera for RoHS/REACH confirmation. Not qualified to AEC-Q100 (commercial temperature grade only).

資料驗證日期： 2026-09-13 — 資料由 XAIPART 元件工程團隊驗證及整理

來源： Distributor, Octopart, Distributor, Distributor, Manufacturer Datasheet, Distributor, Distributor, Manufacturer Product Page, Octopart