EP3SE260H780C4N vs EP3SE260H780C3N 比較

詳細並排比較 EP3SE260H780C4N 由 Intel 與 EP3SE260H780C3N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP3SE260H780C4N EP3SE260H780C3N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND 啟用中
Family Stratix III E (Enhanced) —
Logic Elements 255,000 —
Logic Array Blocks (LABs) 10,200 —
Total RAM Bits 16,672,768 —
Embedded Memory M9K and M144K blocks —
User I/O Pins 488 —
DSP Blocks (18x18 Multipliers) 768 —
PLLs 12 —
Process Node 65 nm CMOS —
Core Voltage 0.86 V to 1.15 V —
Maximum Core Clock Frequency 450 MHz —
封裝 780-ball FCBGA (Flip Chip BGA) 780-BBGA, FCBGA (H780)
安裝類型 Surface Mount Surface Mount
濕度敏感等級 (MSL) 3 (168 hours) [DATA_NEEDED: MSL level per JEDEC J-STD-020]
工作溫度 0C to +85C (commercial) 0 °C to +85 °C (C grade, commercial)
Configuration Method Serial/Parallel via Quartus II SRAM-based, configured via JTAG / passive / active serial / fast passive parallel
Series — Stratix® III E
Logic Elements (LE) — 255,000
Embedded Memory (bits) — 16,672,768
Number of LABs/CLBs — 10,200
User I/Os — 488
Number of Pins / Balls — 780
Process Technology — 40 nm CMOS
Maximum Core Frequency — [DATA_NEEDED: maximum core frequency MHz]
Supply Voltage (VCCINT) — [DATA_NEEDED: VCCINT nominal V]
Transceivers — [DATA_NEEDED: number of embedded transceivers and max data rate]
DSP Blocks — [DATA_NEEDED: number of DSP blocks and precision]
RoHS 狀態 — Compliant (lead-free 'N' suffix)
Design Toolchain — Altera Quartus II (legacy); Intel Quartus Prime

資料表與資源

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