BSC076N04NDATMA1 - 40V 20A 7.6mOhm Dual N-MOSFET | Infineon
MPN： BSC076N04NDATMA1 ✓ 啟用中BSC076N04NDATMA1 概覽
An N-channel MOSFET is a voltage-controlled four-terminal semiconductor switch (gate, drain, source, body) that conducts current when a positive gate-to-source voltage exceeds the threshold voltage (about 4V for this part). The BSC076N04NDATMA1 integrates two independent N-FETs in one package - the array belongs to the metal-oxide-semiconductor field-effect transistor (MOSFET) family, under discrete semiconductors in the power MOSFET hierarchy (MOSFET -> power transistor -> discrete semiconductor -> semiconductor). This architecture is widely used for synchronous rectification, half-bridges, and ORing circuits where two switches share one footprint.
Key features include the OptiMOS™ 3 trench cell design that minimizes RDS(on) x gate charge (Qg) figure of merit, high shot-through immunity due to Qgd/Qgs ratio below 0.8 (reducing cross-conduction risk in half-bridge topologies), Pb-free plating, and RoHS compliance. The dual SuperSO8 package achieves substantially better thermal resistance than competing dual DFN packages while occupying only 5x6 mm of board area. Maximum power dissipation is 2.3W at TA=25 C and 65W at TC=25 C.
The device uses a vertical trench MOSFET structure with N+ source and N- epitaxtial drift region; the low on-resistance is enabled by high cell density. OptiMOS™ 3 also reduces reverse-recovery charge (Qrr) of the intrinsic body diode, improving hard-switched efficiency.
Typical applications include DC-DC converter synchronous buck stages, motor drive half-bridges, eFuse / hot-swap circuits, battery management ORing FETs, and Class-D audio amplifier outputs. The low RDS(on) minimizes conduction loss, while the 40V rating provides ample margin for 12V bus rails with transients.
When designing, ensure VGS drive reaches at least 10V for full RDS(on) specification and keep gate-loop inductance low to suppress ringing. A 4V-7V gate-source absolute maximum should be respected if driven from logic-level signals.
This page synthesizes distributor pricing, verified cross-reference alternatives, and practical PCB layout notes not found in the manufacturer datasheet, making it a one-stop engineering reference for BSC076N04NDATMA1 selection and qualification.
直接替換替代品，適用於 BSC076N04NDATMA1 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： BSC076N04NDATMA1 （相同外形與佔位） — 差異在於 Package, Technology, Operating Temperature Range, MSL Level, Drain-Source Voltage (VDS).
BSC050N04LSGATMA1
✅ 直接替換聯絡詢價
查看資料表 →BSC019N04LSTATMA1
✅ 直接替換聯絡詢價
查看資料表 →IPD50N06S409ATMA2
✅ 直接替換聯絡詢價
查看資料表 →IAUC60N04S6L030HATMA1
✅ 直接替換聯絡詢價
查看資料表 →BSC019N08NS5ATMA1
✅ 直接替換聯絡詢價
查看資料表 →BSC076N04NDATMA1 最大額定值與電氣特性
| Manufacturer | Infineon Technologies |
| Series | OptiMOS 3 |
| Configuration | Dual N-Channel (independent MOSFETs) |
| Drain-Source Voltage (VDS) max | 40 V |
| Continuous Drain Current (ID) | 20 A (Tc) |
| Gate Threshold Voltage (VGS(th)) | 4 V (max, typical) |
| On-Resistance RDS(on) max | 7.6 mOhm |
| Power Dissipation (Ta) | 2.3 W |
| Power Dissipation (Tc) | 65 W |
| Technology | Trench MOSFET (OptiMOS 3) |
| Qgd/Qgs Ratio | < 0.8 (high shot-through immunity) |
| 工作接面溫度 | -55 C to +175 C |
| 封裝 / 外殼 | PG-TDSON-8-4 (SuperSO8, 5x6 mm) |
| 安裝類型 | Surface Mount |
| RoHS / Pb-Free | Compliant (Pb-free plating) |
| FET Type | 2x N-Channel MOSFET array |
BSC076N04NDATMA1 腳位配置
| 腳位 1 | G1 — Gate of MOSFET 1 (lower FET) |
| 腳位 2 | S2 — Source of MOSFET 2 (upper FET) |
| 腳位 3 | G2 — Gate of MOSFET 2 (upper FET) |
| 腳位 4 | D2 — Drain of MOSFET 2 (upper FET) |
| 腳位 5 | D2 — Drain of MOSFET 2 (upper FET) - thermal tab |
| 腳位 6 | S1 — Source of MOSFET 1 (lower FET) |
| 腳位 7 | S1 — Source of MOSFET 1 (lower FET) |
| 腳位 8 | S1 — Source of MOSFET 1 (lower FET) - thermal tab |
| 腳位 EP | D1 — Exposed pad - Drain of MOSFET 1 (lower FET) |
安全工作區 - DC (per MOSFET)
典型應用
BSC076N04NDATMA1 適用於 7 應用s: Synchronous Buck DC-DC Converter, Brushless DC Motor Drive Half-Bridge, Battery ORing / Power Path Management, Class-D Audio Amplifier Output Stage, Hot-Swap / eFuse Controller Switch, Solar Charge Controller / MPPT Stage, Automotive 12V Load Switching.
Synchronous Buck DC-DC Converter
The BSC076N04NDATMA1's 7.6 mOhm RDS(on) and 40V VDS rating make it well-suited for 12V-to-low-voltage synchronous buck stages. Used as both the control FET and synchronous FET in the same SuperSO8 footprint, it keeps the high-side and low-side switches compact and thermally coupled. The Qgd/Qgs ratio below 0.8 reduces shoot-through risk in hard-switched transitions, and the 20A continuous rating handles 30-40A pulse loads typical of VRM applications. Unlike discrete MOSFETs in D2PAK, the dual package saves 60% board area.
推薦
Brushless DC Motor Drive Half-Bridge
For BLDC motor control, the BSC076N04NDATMA1 delivers two N-channel switches per package, ideal for one half-bridge leg of a 3-phase inverter on 12-24V motors. The 20A continuous and 175 C junction rating support peak motor currents up to 60A with proper heatsinking. The 4V gate threshold is compatible with standard 10V gate drive from IRS or IR2x drivers, and the low Qg reduces switching losses at 20-50 kHz PWM frequencies common in motor control.
推薦
Battery ORing / Power Path Management
In redundant battery or USB-PD power-path designs, the BSC076N04NDATMA1 serves as a low-loss ORing FET thanks to its 7.6 mOhm RDS(on) at VGS=10V. Two FETs in one package implement source-to-source ORing with minimal voltage drop - at 5A load, drop is only 38 mV versus 200+ mV for diode ORing. The 40V rating handles 19-20V USB-PD voltages safely, and the SuperSO8 thermal pad provides the low thermal resistance needed for continuous current handling.
推薦
Class-D Audio Amplifier Output Stage
Class-D amplifiers benefit from the BSC076N04NDATMA1's low RDS(on) and matched dual-FET architecture that minimizes dead-time mismatch between high-side and low-side switches. The 7.6 mOhm on-resistance yields 0.5-1% THD at 50W into 4 ohm on a 24V supply. The SuperSO8 package's superior thermal resistance over DFN alternatives keeps junction temperature manageable at high audio power levels, and the 40V rating handles 36V peak amplifier outputs.
推薦
Hot-Swap / eFuse Controller Switch
For 12V or 24V hot-swap and eFuse circuits, the BSC076N04NDATMA1's 7.6 mOhm RDS(on) keeps steady-state voltage drop under 200 mV at 20A, while the 40V VDS absorbs inrush transients during board insertion. The dual SuperSO8 package supports either dual parallel paths or back-to-back configurations for true isolation. Designers combine it with current-sense amplifiers and gate ramp controllers for soft-start, leveraging Infineon's full ecosystem.
推薦
Solar Charge Controller / MPPT Stage
In low-power solar MPPT converters, the BSC076N04NDATMA1 handles 30V open-circuit panel voltages with margin, and its 7.6 mOhm RDS(on) minimizes conduction loss on the synchronous rectifier side of a buck or buck-boost topology. The dual N-FET configuration simplifies PCB layout for synchronous rectification at switching frequencies of 100-300 kHz. The 175 C junction rating supports harsh outdoor enclosure conditions with limited active cooling.
推薦
Automotive 12V Load Switching
In automotive body electronics, the BSC076N04NDATMA1's 40V VDS handles load-dump transients up to 35V on 12V buses, while the 175 C junction rating supports under-hood thermal stress. The dual SuperSO8 footprint reduces PCB area versus two discrete D2PAK FETs, critical for space-constrained BCM modules. Designers typically pair it with smart drivers that include reverse-battery and overcurrent protection per automotive load-switch standards.
推薦
推薦產品摘要
工程參考資料，適用於 BSC076N04NDATMA1 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | BSC050N04LSGATMA1 | BSC019N04LSTATMA1 | IPD50N06S409ATMA2 | IAUC60N04S6L030HATMA1 | BSC019N08NS5ATMA1 |
|---|---|---|---|---|---|---|
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies |
| Package | PG-TDSON-8-4 (SuperSO8 5x6) | PG-TDSON-8-4 (SuperSO8 5x6) - same | PG-TDSON-8-4 (SuperSO8 5x6) - same | PG-TDSON-8-4 (SuperSO8 5x6) - same | PG-TDSON-8-4 (SuperSO8 5x6) - same | PG-TDSON-8-4 (SuperSO8 5x6) - same |
| VDS max | 40 V | 40 V | 40 V | 60 V | 40 V | 80 V |
| ID max (Tc) | 20 A | 25 A | 30 A | 50 A | 60 A | 100 A |
| RDS(on) max | 7.6 mOhm | 5.0 mOhm | 1.9 mOhm | 4.0 mOhm | 3.0 mOhm | 1.9 mOhm |
| Technology | OptiMOS 3 | OptiMOS 5 | OptiMOS 5 | OptiMOS 2 | OptiMOS 6 | OptiMOS 5 |
| Gate Threshold VGS(th) max | 4 V | 3.5 V | 3.5 V | 4 V | 3.5 V | 3.5 V |
| Max Junction Temp | 175 C | 175 C | 175 C | 175 C | 175 C | 175 C |
| Configuration | Dual N-Channel | Dual N-Channel | Dual N-Channel | Single N-Channel | Dual N-Channel | Single N-Channel |
主要差異化特點
- Dual N-FET integration saves PCB area versus two discrete D2PAK devices (對比IRFB3207ZPBF (single TO-220 FET))
- OptiMOS 3 technology with proven shot-through immunity (對比BSC019N08NS5ATMA1 (OptiMOS 5, higher VDS))
- Balanced cost-performance ratio for 40V dual-FET designs (對比BSC019N04LSTATMA1 (1.9 mOhm, OptiMOS 5))
設計說明
Estimated: at 10A continuous per FET with VGS=10V, conduction loss is I^2 * R = 100 * 0.0076 = 0.76W per FET (1.52W total). With the SuperSO8 RthJA of approximately 50 C/W on a 1 oz 1 in^2 copper pour, junction rise is 50 * 1.52 = 76 C above ambient. For 15A continuous operation, loss rises to 1.71W per FET (3.42W total) producing a 171 C rise - implement forced airflow or 2-3 in^2 copper to stay within thermal limits.
The exposed pad (D1) must be soldered to a top-layer copper pour that is thermally tied to inner power planes with at least 4 thermal vias (0.3 mm drill, 1 mm pitch). Keep the gate-trace impedance below 5 nH by routing directly from the driver IC to the gate pin with a 10-100 ohm series damping resistor to suppress ringing. Place a 10 kohm gate-source pull-down resistor on each gate to prevent unintended turn-on during power-up.
Do not drive VGS above the absolute maximum of +/-20V (per datasheet); use a 12-15V zener clamp if the driver supply is 18V or higher. The 4V gate threshold means logic-level 3.3V GPIO signals will NOT fully enhance the FET - always use a gate driver for high-current applications. Also observe the body diode reverse-recovery charge (Qrr) when used in hard-switched topologies; for soft-switched designs the body diode Qrr is irrelevant.
Keep the source-return path of each FET short and wide to minimize parasitic inductance that causes voltage overshoot during turn-off. Use a star-ground connection for the gate driver return rather than daisy-chaining through the source pin. Place input/output capacitors of the DC-DC stage within 5 mm of the drain/source pads to reduce AC loop inductance.
合規資訊
Pb-free plating per Infineon datasheet; RoHS compliant. AEC-Q100 qualification status not explicitly stated - verify with Infineon for automotive designs requiring this certification.
