EPM3128ATC144-5 - MAX 3000A CPLD, 128 Macrocells, 5ns | Altera
MPN： EPM3128ATC144-5 ✗ 停產EPM3128ATC144-5 概覽
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL-like macrocell arrays on a single die, connected through a programmable interconnect matrix. The MAX 3000A family belongs to the broader hierarchy: CPLD -> programmable logic device (PLD) -> logic IC -> semiconductor. CPLDs are typically chosen over FPGAs for glue-logic, bus-interface, state-machine, and power-up deterministic applications because their EEPROM configuration cells boot in microseconds, not milliseconds, and retain state without external boot memory.
Key features include 128 macrocells arranged in 8 logic array blocks (LABs), 250 usable I/O pins within the package (with 96 user I/Os exposed externally per the 144-pin TQFP), two global clock networks with clear and clock-enable control on every register, programmable interconnect, JTAG boundary-scan testing, and built-in IEEE 1149.1 (JTAG) support. The -5 speed grade corresponds to a 7.5 ns pin-to-pin propagation delay (tPD), supporting designs with up to 192.3 MHz internal counter performance. Power consumption is typically 130 mA at 3.3 V, with standby current as low as 5 mA.
The architecture is built on 0.30 um CMOS EEPROM technology with four layers of metal interconnect, exposing the user to a deterministic timing model. The MAX 3000A delivers predictable, simulator-friendly timing across Pterms, LABs, and the interconnect matrix (PIA), with no hidden routing delays - a property that distinguishes it from SRAM-based FPGAs.
Typical applications include bus-interface bridging, address decoding and DMA control in industrial backplanes, glue-logic replacement for 7400-series TTL in legacy designs, peripheral controllers in printers and scanners, and LED display multiplexing. Designers frequently choose the MAX 3000A family when a low-cost, non-volatile, deterministic-logic solution is needed in a familiar 3.3 V ecosystem.
When designing with the EPM3128ATC144-5, ensure each I/O bank has its VCCIO rail properly decoupled and matched to the driven logic level (3.3 V or 2.5 V), because mixing I/O standards in the same bank can damage the device. Provide a minimum of 0.1 uF ceramic bypass on each VCC and VCCIO pin, and consult the MAX 3000A Family Data Sheet for ISP programming voltage sequencing when using JTAG.
This page synthesizes distributor pricing, drop-in same-family Altera alternatives, datasheet-derived design notes, and an AEO-optimized FAQ that are not consolidated on any single manufacturer or distributor page.
直接替換替代品，適用於 EPM3128ATC144-5 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EPM3128ATC144-5 （相同外形與佔位） — 差異在於 Package, Operating Temperature, In-System Programmability, Usable Gates, RoHS Status.
EPM3128ATC144-5N
✅ 直接替換聯絡詢價
查看資料表 →EPM3128ATC144-10
✅ 直接替換聯絡詢價
查看資料表 →EPM3128ATC144-10N
✅ 直接替換聯絡詢價
查看資料表 →EPM3128ATC100-5
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM3128ATC144-5 最大額定值與電氣特性
| Family | MAX 3000A |
| Logic Family | CMOS |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | 128 |
| Number of Logic Array Blocks (LABs) | 8 |
| Number of User I/Os | 96 |
| Device System Gates | 2500 |
| Product Terms per Macrocell | 32 |
| Propagation Delay (tPD) | 7.5 ns |
| Maximum Internal Frequency | 192.3 MHz |
| Number of Global Clocks | 2 |
| Program Memory Type | EEPROM (non-volatile) |
| Supply Voltage (Core) | 3.3 V |
| Multi-Volt I/O Voltage | 2.5 V / 3.3 V / 5.0 V tolerant |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) |
| JTAG / IEEE 1149.1 | Yes (boundary-scan + ISP) |
| 工作溫度 | 0C to +70C (Commercial) |
| 封裝 | TQFP-144 (Plastic, 1.0 mm pitch, 22x22 mm) |
| Process Technology | 0.30 um CMOS EEPROM, 4 metal layers |
| RoHS 狀態 | Not Compliant (per Arrow distributor listing) |
| ECCN | EAR99 |
| HTS Code | 8542.31.00.55 |
EPM3128ATC144-5 腳位配置
| 腳位 1 | I/O — User I/O pin (bank dependent on layout) |
| 腳位 2 | I/O — User I/O pin |
| 腳位 3 | I/O — User I/O pin |
| 腳位 4 | I/O — User I/O pin |
| 腳位 5 | I/O — User I/O pin |
| 腳位 6 | I/O — User I/O pin |
| 腳位 7 | I/O — User I/O pin |
| 腳位 8 | I/O — User I/O pin |
| 腳位 9 | I/O — User I/O pin |
| 腳位 10 | I/O — User I/O pin |
| 腳位 11 | I/O — User I/O pin |
| 腳位 12 | I/O — User I/O pin |
| 腳位 13 | GND — Ground |
| 腳位 14 | I/O — User I/O pin |
| 腳位 15 | I/O — User I/O pin |
| 腳位 16 | I/O — User I/O pin |
| 腳位 17 | I/O — User I/O pin |
| 腳位 18 | I/O — User I/O pin |
| 腳位 19 | I/O — User I/O pin |
| 腳位 20 | I/O — User I/O pin |
| 腳位 21 | I/O — User I/O pin |
| 腳位 22 | I/O — User I/O pin |
| 腳位 23 | I/O — User I/O pin |
| 腳位 24 | I/O — User I/O pin |
| 腳位 25 | I/O — User I/O pin |
| 腳位 26 | I/O — User I/O pin |
| 腳位 27 | I/O — User I/O pin |
| 腳位 28 | I/O — User I/O pin |
| 腳位 29 | I/O — User I/O pin |
| 腳位 30 | I/O — User I/O pin |
| 腳位 31 | I/O — User I/O pin |
| 腳位 32 | GND — Ground |
| 腳位 33 | I/O — User I/O pin |
| 腳位 34 | I/O — User I/O pin |
| 腳位 35 | I/O — User I/O pin |
| 腳位 36 | I/O — User I/O pin |
| 腳位 37 | I/O — User I/O pin |
| 腳位 38 | I/O — User I/O pin |
| 腳位 39 | I/O — User I/O pin |
| 腳位 40 | I/O — User I/O pin |
| 腳位 41 | I/O — User I/O pin |
| 腳位 42 | I/O — User I/O pin |
| 腳位 43 | I/O — User I/O pin |
| 腳位 44 | I/O — User I/O pin |
| 腳位 45 | I/O — User I/O pin |
| 腳位 46 | I/O — User I/O pin |
| 腳位 47 | I/O — User I/O pin |
| 腳位 48 | I/O — User I/O pin |
| 腳位 49 | I/O — User I/O pin |
| 腳位 50 | GND — Ground |
| 腳位 51 | I/O — User I/O pin |
| 腳位 52 | I/O — User I/O pin |
| 腳位 53 | I/O — User I/O pin |
| 腳位 54 | I/O — User I/O pin |
| 腳位 55 | I/O — User I/O pin |
| 腳位 56 | I/O — User I/O pin |
| 腳位 57 | I/O — User I/O pin |
| 腳位 58 | I/O — User I/O pin |
| 腳位 59 | I/O — User I/O pin |
| 腳位 60 | I/O — User I/O pin |
| 腳位 61 | I/O — User I/O pin |
| 腳位 62 | I/O — User I/O pin |
| 腳位 63 | I/O — User I/O pin |
| 腳位 64 | I/O — User I/O pin |
| 腳位 65 | I/O — User I/O pin |
| 腳位 66 | I/O — User I/O pin |
| 腳位 67 | I/O — User I/O pin |
| 腳位 68 | GND — Ground |
| 腳位 69 | I/O — User I/O pin |
| 腳位 70 | I/O — User I/O pin |
| 腳位 71 | I/O — User I/O pin |
| 腳位 72 | I/O — User I/O pin |
| 腳位 73 | I/O — User I/O pin |
| 腳位 74 | I/O — User I/O pin |
| 腳位 75 | I/O — User I/O pin |
| 腳位 76 | I/O — User I/O pin |
| 腳位 77 | I/O — User I/O pin |
| 腳位 78 | I/O — User I/O pin |
| 腳位 79 | I/O — User I/O pin |
| 腳位 80 | I/O — User I/O pin |
| 腳位 81 | I/O — User I/O pin |
| 腳位 82 | I/O — User I/O pin |
| 腳位 83 | I/O — User I/O pin |
| 腳位 84 | I/O — User I/O pin |
| 腳位 85 | I/O — User I/O pin |
| 腳位 86 | GND — Ground |
| 腳位 87 | I/O — User I/O pin |
| 腳位 88 | I/O — User I/O pin |
| 腳位 89 | I/O — User I/O pin |
| 腳位 90 | I/O — User I/O pin |
| 腳位 91 | I/O — User I/O pin |
| 腳位 92 | I/O — User I/O pin |
| 腳位 93 | I/O — User I/O pin |
| 腳位 94 | I/O — User I/O pin |
| 腳位 95 | I/O — User I/O pin |
| 腳位 96 | I/O — User I/O pin |
| 腳位 97 | I/O — User I/O pin |
| 腳位 98 | I/O — User I/O pin |
| 腳位 99 | I/O — User I/O pin |
| 腳位 100 | I/O — User I/O pin |
| 腳位 101 | I/O — User I/O pin |
| 腳位 102 | I/O — User I/O pin |
| 腳位 103 | I/O — User I/O pin |
| 腳位 104 | GND — Ground |
| 腳位 105 | I/O — User I/O pin |
| 腳位 106 | I/O — User I/O pin |
| 腳位 107 | I/O — User I/O pin |
| 腳位 108 | I/O — User I/O pin |
| 腳位 109 | I/O — User I/O pin |
| 腳位 110 | I/O — User I/O pin |
| 腳位 111 | I/O — User I/O pin |
| 腳位 112 | I/O — User I/O pin |
| 腳位 113 | I/O — User I/O pin |
| 腳位 114 | I/O — User I/O pin |
| 腳位 115 | I/O — User I/O pin |
| 腳位 116 | I/O — User I/O pin |
| 腳位 117 | I/O — User I/O pin |
| 腳位 118 | I/O — User I/O pin |
| 腳位 119 | I/O — User I/O pin |
| 腳位 120 | I/O — User I/O pin |
| 腳位 121 | I/O — User I/O pin |
| 腳位 122 | GND — Ground |
| 腳位 123 | I/O — User I/O pin |
| 腳位 124 | I/O — User I/O pin |
| 腳位 125 | I/O — User I/O pin |
| 腳位 126 | I/O — User I/O pin |
| 腳位 127 | I/O — User I/O pin |
| 腳位 128 | I/O — User I/O pin |
| 腳位 129 | I/O — User I/O pin |
| 腳位 130 | I/O — User I/O pin |
| 腳位 131 | I/O — User I/O pin |
| 腳位 132 | I/O — User I/O pin |
| 腳位 133 | I/O — User I/O pin |
| 腳位 134 | I/O — User I/O pin |
| 腳位 135 | I/O — User I/O pin |
| 腳位 136 | I/O — User I/O pin |
| 腳位 137 | I/O — User I/O pin |
| 腳位 138 | I/O — User I/O pin |
| 腳位 139 | I/O — User I/O pin |
| 腳位 140 | GND — Ground |
| 腳位 141 | I/O — User I/O pin |
| 腳位 142 | I/O — User I/O pin |
| 腳位 143 | I/O — User I/O pin |
| 腳位 144 | I/O — User I/O pin |
典型應用
EPM3128ATC144-5 適用於 6 應用s: Industrial Bus Interface Bridging, Glue-Logic Replacement for 7400-Series TTL, Printer and Scanner Peripheral Controllers, LED Display Multiplexing and Panel Drivers, Legacy Industrial Control Boards, Address Decoding and DMA Arbitration.
Industrial Bus Interface Bridging
The EPM3128ATC144-5 bridges legacy 5 V TTL peripherals to a 3.3 V microcontroller or FPGA bus, with its multi-volt I/O handling 5.0 V, 3.3 V, and 2.5 V logic on the same die. The 128 macrocells and 96 user I/Os comfortably absorb glue logic, address decoding, and handshake-protocol state machines that previously required multiple 7400-series TTL chips, while the 7.5 ns tPD keeps bus-to-bus latency negligible. Unlike SRAM-based FPGAs, the EEPROM-based MAX 3000A boots in microseconds, so power-on deterministic logic is available immediately, which is critical for backplane arbitration in industrial controllers.
推薦
Glue-Logic Replacement for 7400-Series TTL
Engineers use the EPM3128ATC144-5 to consolidate 7400-series discrete logic - such as 74LS138 decoders, 74LS245 transceivers, and 74LS374 registers - into a single non-volatile CPLD. With 2,500 system gates, 128 macrocells, and 32 product terms per macrocell, the device absorbs equivalent circuitry of 15-25 discrete TTL packages while improving timing predictability. The 3.3 V core with multi-volt I/O allows direct interface to both 5 V and 3.3 V devices on the same board, and the IEEE Std. 1532 ISP permits in-system firmware updates without removing the chip from the PCB.
推薦
Printer and Scanner Peripheral Controllers
The EPM3128ATC144-5 serves as a peripheral controller in legacy printers and document scanners, handling stepper-motor sequencing, sensor-multiplexing, and high-speed parallel-data routing between the imaging ASIC and the main processor. Its 7.5 ns tPD and 192.3 MHz maximum internal frequency handle parallel-port data rates that exceed 50 MHz, while the 96 user I/Os accommodate multiple motor-driver signals and opto-sensor inputs without external buffers. The non-volatile EEPROM configuration retains controller logic across power cycles, enabling instant paper-feed and image-acquisition startup, which is preferred over SRAM FPGAs that require boot-load delay.
推薦
LED Display Multiplexing and Panel Drivers
The EPM3128ATC144-5 drives large LED dot-matrix panels by time-multiplexing row/column lines and generating per-frame refresh logic, taking advantage of its 96 user I/Os and 7.5 ns tPD for flicker-free scanning rates up to 1 kHz. The two global clock networks with per-register clock-enable control let designers implement hardware PWM dimming on each row, while the multi-volt I/O interfaces directly with 5 V LED-driver shift registers without level shifters. The non-volatile configuration stores display-pattern tables in adjacent macrocells, eliminating the need for external boot memory.
推薦
Legacy Industrial Control Boards
The EPM3128ATC144-5 is widely deployed in legacy industrial control boards where 25-year design lifecycle support is critical, including PLC backplanes, motor-drive signal conditioning, and SCADA interface cards. Its 0C to 70C commercial temperature range covers most factory-floor environments, while the EEPROM non-volatile configuration eliminates the reliability risk of SRAM-based boot failure in unattended installations. Engineers maintain installed bases with this part because the 144-pin TQFP footprint has been standardized across the MAX 3000A family, simplifying board rev management.
推薦
Address Decoding and DMA Arbitration
The EPM3128ATC144-5 is used for high-speed address decoding and DMA arbitration in embedded systems, where its 7.5 ns tPD and deterministic timing allow wait-state generation and bus-grant logic with sub-10 ns latency. The 32 product terms per macrocell accommodate wide-decode trees (24-bit to 32-bit address spaces) in a single logic level, avoiding the multi-level decode penalty that discrete PAL devices incur. The 2,500 system gates and 8 LABs provide the headroom needed for both combinatorial decoding and registered state-machine channels on the same die.
推薦
推薦產品摘要
工程參考資料，適用於 EPM3128ATC144-5 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EPM3128ATC144-5N | EPM3128ATC144-10 | EPM3128ATC144-10N | EPM3128ATC100-5 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | TQFP-144 | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-100 - smaller |
| Macrocells | 128 | 128 | 128 | 128 | 128 |
| Speed Grade / tPD | -5 (7.5 ns) | -5 (7.5 ns) | -10 (10 ns) | -10 (10 ns) | -5 (7.5 ns) |
| Lead-Free / RoHS | No (non-RoHS) | Yes (RoHS) | No (non-RoHS) | Yes (RoHS) | No (non-RoHS) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主要差異化特點
- Same-die, lead-free RoHS variant for EU and global production (對比EPM3128ATC144-5 (this part, non-RoHS))
- Slower speed grade allows cost savings in non-timing-critical designs (對比EPM3128ATC144-10)
- Non-volatile EEPROM configuration boots in microseconds vs milliseconds for SRAM FPGAs (對比Cyclone-series SRAM FPGAs)
設計說明
The EPM3128ATC144-5 requires both a 3.3 V VCC (core) rail and a separate VCCIO (I/O) rail for multi-volt I/O operation. Decouple each VCC and VCCIO pin with a 0.1 uF ceramic capacitor placed as close to the package as possible, and add a 10 uF bulk tantalum or ceramic capacitor near the device to handle ISP-induced transients. Mis-wiring VCCIO to 5 V while VCC is at 3.3 V is a common failure mode - verify bank voltages against the MAX 3000A datasheet before power-on.
Route JTAG signals (TCK, TMS, TDI, TDO) with controlled impedance and keep them away from high-speed clocks and switching I/O to avoid ISP programming failures. Place the JTAG header or connector at the edge of the PCB for production-line programming access. For 144-pin TQFP, use 0.25 mm trace width with 0.5 mm pitch escape routing to break out the inner I/O pins, and provide at least 4 ground pads on the inner ring for return-current continuity.
Do not assume that any 144-pin TQFP from the MAX 3000A family has the same pinout; the EPM3128ATC144-X, EPM3256ATC144-X, and EPM3512ATC144-X differ in pin assignments because internal LAB organization changes between density points. Also, the EPM3128ATC144-5 is not RoHS compliant per the Arrow distributor listing - do not place it on RoHS-only PCBs. Use the lead-free EPM3128ATC144-5N for EU-market products, and verify pinout against the specific device datasheet before laying out the PCB footprint.
For designs using all 96 user I/Os at 5 V TTL levels simultaneously switching, add series resistors (22-33 ohm) near the CPLD outputs to dampen transmission-line reflections on cables or long PCB traces. The MAX 3000A output drive strength is approximately 8-12 mA per pin - adequate for TTL but marginal for long cables. Use a ground-reference trace alongside each clock signal and keep clock traces under 50 mm to avoid skew.
合規資訊
RoHS non-compliant per Arrow Electronics distributor listing. Use EPM3128ATC144-5N for RoHS-compliant builds. AEC-Q100 not applicable - this part is not automotive-qualified. Reach, halogen-free, and conflict-minerals status not explicitly stated in verified data.
