EPM3128ATC144-5 - MAX 3000A CPLD, 128 Macrocells, 5ns | Altera
MPN: EPM3128ATC144-5 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.75 | $8.75 |
| 10 | $7.45 | $74.50 |
| 100 | $6.2 | $620.00 |
| 500 | $5.4 | $2,700.00 |
| 1,000 | $4.85 | $4,850.00 |
Drop-in alternatives for EPM3128ATC144-5 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM3128ATC144-5N
✅ Drop-In✓ In Stock
$13.75 / Unit
View Datasheet →EPM3128ATC144-10
✅ Drop-In✓ In Stock
$6.2 / Unit
View Datasheet →EPM3128ATC144-10N
✅ Drop-In✓ In Stock
$6.56 / Unit
View Datasheet →EPM3128ATC100-5
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$15.43 / Unit
View Datasheet →EPM3128ATC144-5 Maximum Ratings & Electrical Characteristics
| Family | MAX 3000A |
| Logic Family | CMOS |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | 128 |
| Number of Logic Array Blocks (LABs) | 8 |
| Number of User I/Os | 96 |
| Device System Gates | 2500 |
| Product Terms per Macrocell | 32 |
| Propagation Delay (tPD) | 7.5 ns |
| Maximum Internal Frequency | 192.3 MHz |
| Number of Global Clocks | 2 |
| Program Memory Type | EEPROM (non-volatile) |
| Supply Voltage (Core) | 3.3 V |
| Multi-Volt I/O Voltage | 2.5 V / 3.3 V / 5.0 V tolerant |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) |
| JTAG / IEEE 1149.1 | Yes (boundary-scan + ISP) |
| Operating Temperature | 0C to +70C (Commercial) |
| Package | TQFP-144 (Plastic, 1.0 mm pitch, 22x22 mm) |
| Process Technology | 0.30 um CMOS EEPROM, 4 metal layers |
| RoHS Status | Not Compliant (per Arrow distributor listing) |
| ECCN | EAR99 |
| HTS Code | 8542.31.00.55 |
EPM3128ATC144-5 Pin Configuration
| Pin 1 | I/O — User I/O pin (bank dependent on layout) |
| Pin 2 | I/O — User I/O pin |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | I/O — User I/O pin |
| Pin 7 | I/O — User I/O pin |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | I/O — User I/O pin |
| Pin 10 | I/O — User I/O pin |
| Pin 11 | I/O — User I/O pin |
| Pin 12 | I/O — User I/O pin |
| Pin 13 | GND — Ground |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | I/O — User I/O pin |
| Pin 16 | I/O — User I/O pin |
| Pin 17 | I/O — User I/O pin |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | I/O — User I/O pin |
| Pin 20 | I/O — User I/O pin |
| Pin 21 | I/O — User I/O pin |
| Pin 22 | I/O — User I/O pin |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | I/O — User I/O pin |
| Pin 26 | I/O — User I/O pin |
| Pin 27 | I/O — User I/O pin |
| Pin 28 | I/O — User I/O pin |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | I/O — User I/O pin |
| Pin 31 | I/O — User I/O pin |
| Pin 32 | GND — Ground |
| Pin 33 | I/O — User I/O pin |
| Pin 34 | I/O — User I/O pin |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | I/O — User I/O pin |
| Pin 37 | I/O — User I/O pin |
| Pin 38 | I/O — User I/O pin |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | I/O — User I/O pin |
| Pin 41 | I/O — User I/O pin |
| Pin 42 | I/O — User I/O pin |
| Pin 43 | I/O — User I/O pin |
| Pin 44 | I/O — User I/O pin |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | I/O — User I/O pin |
| Pin 47 | I/O — User I/O pin |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | GND — Ground |
| Pin 51 | I/O — User I/O pin |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | I/O — User I/O pin |
| Pin 54 | I/O — User I/O pin |
| Pin 55 | I/O — User I/O pin |
| Pin 56 | I/O — User I/O pin |
| Pin 57 | I/O — User I/O pin |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | I/O — User I/O pin |
| Pin 61 | I/O — User I/O pin |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | I/O — User I/O pin |
| Pin 64 | I/O — User I/O pin |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | I/O — User I/O pin |
| Pin 67 | I/O — User I/O pin |
| Pin 68 | GND — Ground |
| Pin 69 | I/O — User I/O pin |
| Pin 70 | I/O — User I/O pin |
| Pin 71 | I/O — User I/O pin |
| Pin 72 | I/O — User I/O pin |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | I/O — User I/O pin |
| Pin 75 | I/O — User I/O pin |
| Pin 76 | I/O — User I/O pin |
| Pin 77 | I/O — User I/O pin |
| Pin 78 | I/O — User I/O pin |
| Pin 79 | I/O — User I/O pin |
| Pin 80 | I/O — User I/O pin |
| Pin 81 | I/O — User I/O pin |
| Pin 82 | I/O — User I/O pin |
| Pin 83 | I/O — User I/O pin |
| Pin 84 | I/O — User I/O pin |
| Pin 85 | I/O — User I/O pin |
| Pin 86 | GND — Ground |
| Pin 87 | I/O — User I/O pin |
| Pin 88 | I/O — User I/O pin |
| Pin 89 | I/O — User I/O pin |
| Pin 90 | I/O — User I/O pin |
| Pin 91 | I/O — User I/O pin |
| Pin 92 | I/O — User I/O pin |
| Pin 93 | I/O — User I/O pin |
| Pin 94 | I/O — User I/O pin |
| Pin 95 | I/O — User I/O pin |
| Pin 96 | I/O — User I/O pin |
| Pin 97 | I/O — User I/O pin |
| Pin 98 | I/O — User I/O pin |
| Pin 99 | I/O — User I/O pin |
| Pin 100 | I/O — User I/O pin |
| Pin 101 | I/O — User I/O pin |
| Pin 102 | I/O — User I/O pin |
| Pin 103 | I/O — User I/O pin |
| Pin 104 | GND — Ground |
| Pin 105 | I/O — User I/O pin |
| Pin 106 | I/O — User I/O pin |
| Pin 107 | I/O — User I/O pin |
| Pin 108 | I/O — User I/O pin |
| Pin 109 | I/O — User I/O pin |
| Pin 110 | I/O — User I/O pin |
| Pin 111 | I/O — User I/O pin |
| Pin 112 | I/O — User I/O pin |
| Pin 113 | I/O — User I/O pin |
| Pin 114 | I/O — User I/O pin |
| Pin 115 | I/O — User I/O pin |
| Pin 116 | I/O — User I/O pin |
| Pin 117 | I/O — User I/O pin |
| Pin 118 | I/O — User I/O pin |
| Pin 119 | I/O — User I/O pin |
| Pin 120 | I/O — User I/O pin |
| Pin 121 | I/O — User I/O pin |
| Pin 122 | GND — Ground |
| Pin 123 | I/O — User I/O pin |
| Pin 124 | I/O — User I/O pin |
| Pin 125 | I/O — User I/O pin |
| Pin 126 | I/O — User I/O pin |
| Pin 127 | I/O — User I/O pin |
| Pin 128 | I/O — User I/O pin |
| Pin 129 | I/O — User I/O pin |
| Pin 130 | I/O — User I/O pin |
| Pin 131 | I/O — User I/O pin |
| Pin 132 | I/O — User I/O pin |
| Pin 133 | I/O — User I/O pin |
| Pin 134 | I/O — User I/O pin |
| Pin 135 | I/O — User I/O pin |
| Pin 136 | I/O — User I/O pin |
| Pin 137 | I/O — User I/O pin |
| Pin 138 | I/O — User I/O pin |
| Pin 139 | I/O — User I/O pin |
| Pin 140 | GND — Ground |
| Pin 141 | I/O — User I/O pin |
| Pin 142 | I/O — User I/O pin |
| Pin 143 | I/O — User I/O pin |
| Pin 144 | I/O — User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3128ATC144-5 is suitable for 6 applications: Industrial Bus Interface Bridging, Glue-Logic Replacement for 7400-Series TTL, Printer and Scanner Peripheral Controllers, LED Display Multiplexing and Panel Drivers, Legacy Industrial Control Boards, Address Decoding and DMA Arbitration.
Industrial Bus Interface Bridging
The EPM3128ATC144-5 bridges legacy 5 V TTL peripherals to a 3.3 V microcontroller or FPGA bus, with its multi-volt I/O handling 5.0 V, 3.3 V, and 2.5 V logic on the same die. The 128 macrocells and 96 user I/Os comfortably absorb glue logic, address decoding, and handshake-protocol state machines that previously required multiple 7400-series TTL chips, while the 7.5 ns tPD keeps bus-to-bus latency negligible. Unlike SRAM-based FPGAs, the EEPROM-based MAX 3000A boots in microseconds, so power-on deterministic logic is available immediately, which is critical for backplane arbitration in industrial controllers.
Recommended
Glue-Logic Replacement for 7400-Series TTL
Engineers use the EPM3128ATC144-5 to consolidate 7400-series discrete logic - such as 74LS138 decoders, 74LS245 transceivers, and 74LS374 registers - into a single non-volatile CPLD. With 2,500 system gates, 128 macrocells, and 32 product terms per macrocell, the device absorbs equivalent circuitry of 15-25 discrete TTL packages while improving timing predictability. The 3.3 V core with multi-volt I/O allows direct interface to both 5 V and 3.3 V devices on the same board, and the IEEE Std. 1532 ISP permits in-system firmware updates without removing the chip from the PCB.
Recommended
Printer and Scanner Peripheral Controllers
The EPM3128ATC144-5 serves as a peripheral controller in legacy printers and document scanners, handling stepper-motor sequencing, sensor-multiplexing, and high-speed parallel-data routing between the imaging ASIC and the main processor. Its 7.5 ns tPD and 192.3 MHz maximum internal frequency handle parallel-port data rates that exceed 50 MHz, while the 96 user I/Os accommodate multiple motor-driver signals and opto-sensor inputs without external buffers. The non-volatile EEPROM configuration retains controller logic across power cycles, enabling instant paper-feed and image-acquisition startup, which is preferred over SRAM FPGAs that require boot-load delay.
Recommended
LED Display Multiplexing and Panel Drivers
The EPM3128ATC144-5 drives large LED dot-matrix panels by time-multiplexing row/column lines and generating per-frame refresh logic, taking advantage of its 96 user I/Os and 7.5 ns tPD for flicker-free scanning rates up to 1 kHz. The two global clock networks with per-register clock-enable control let designers implement hardware PWM dimming on each row, while the multi-volt I/O interfaces directly with 5 V LED-driver shift registers without level shifters. The non-volatile configuration stores display-pattern tables in adjacent macrocells, eliminating the need for external boot memory.
Recommended
Legacy Industrial Control Boards
The EPM3128ATC144-5 is widely deployed in legacy industrial control boards where 25-year design lifecycle support is critical, including PLC backplanes, motor-drive signal conditioning, and SCADA interface cards. Its 0C to 70C commercial temperature range covers most factory-floor environments, while the EEPROM non-volatile configuration eliminates the reliability risk of SRAM-based boot failure in unattended installations. Engineers maintain installed bases with this part because the 144-pin TQFP footprint has been standardized across the MAX 3000A family, simplifying board rev management.
Recommended
Address Decoding and DMA Arbitration
The EPM3128ATC144-5 is used for high-speed address decoding and DMA arbitration in embedded systems, where its 7.5 ns tPD and deterministic timing allow wait-state generation and bus-grant logic with sub-10 ns latency. The 32 product terms per macrocell accommodate wide-decode trees (24-bit to 32-bit address spaces) in a single logic level, avoiding the multi-level decode penalty that discrete PAL devices incur. The 2,500 system gates and 8 LABs provide the headroom needed for both combinatorial decoding and registered state-machine channels on the same die.
Recommended
Recommended Products Summary
Engineering reference data for EPM3128ATC144-5 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3128ATC144-5N | EPM3128ATC144-10 | EPM3128ATC144-10N | EPM3128ATC100-5 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | TQFP-144 | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-100 - smaller |
| Macrocells | 128 | 128 | 128 | 128 | 128 |
| Speed Grade / tPD | -5 (7.5 ns) | -5 (7.5 ns) | -10 (10 ns) | -10 (10 ns) | -5 (7.5 ns) |
| Maximum Internal Frequency | 192.3 MHz | 192.3 MHz | [DATA_NEEDED] | [DATA_NEEDED] | 192.3 MHz |
| User I/Os | 96 | 96 | 96 | 96 | [DATA_NEEDED] |
| Lead-Free / RoHS | No (non-RoHS) | Yes (RoHS) | No (non-RoHS) | Yes (RoHS) | No (non-RoHS) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Approx. Qty-1 Price (USD) | 8.75 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Same-die, lead-free RoHS variant for EU and global production (vs EPM3128ATC144-5 (this part, non-RoHS))
- Slower speed grade allows cost savings in non-timing-critical designs (vs EPM3128ATC144-10)
- Non-volatile EEPROM configuration boots in microseconds vs milliseconds for SRAM FPGAs (vs Cyclone-series SRAM FPGAs)
Design Notes
The EPM3128ATC144-5 requires both a 3.3 V VCC (core) rail and a separate VCCIO (I/O) rail for multi-volt I/O operation. Decouple each VCC and VCCIO pin with a 0.1 uF ceramic capacitor placed as close to the package as possible, and add a 10 uF bulk tantalum or ceramic capacitor near the device to handle ISP-induced transients. Mis-wiring VCCIO to 5 V while VCC is at 3.3 V is a common failure mode - verify bank voltages against the MAX 3000A datasheet before power-on.
Route JTAG signals (TCK, TMS, TDI, TDO) with controlled impedance and keep them away from high-speed clocks and switching I/O to avoid ISP programming failures. Place the JTAG header or connector at the edge of the PCB for production-line programming access. For 144-pin TQFP, use 0.25 mm trace width with 0.5 mm pitch escape routing to break out the inner I/O pins, and provide at least 4 ground pads on the inner ring for return-current continuity.
Do not assume that any 144-pin TQFP from the MAX 3000A family has the same pinout; the EPM3128ATC144-X, EPM3256ATC144-X, and EPM3512ATC144-X differ in pin assignments because internal LAB organization changes between density points. Also, the EPM3128ATC144-5 is not RoHS compliant per the Arrow distributor listing - do not place it on RoHS-only PCBs. Use the lead-free EPM3128ATC144-5N for EU-market products, and verify pinout against the specific device datasheet before laying out the PCB footprint.
For designs using all 96 user I/Os at 5 V TTL levels simultaneously switching, add series resistors (22-33 ohm) near the CPLD outputs to dampen transmission-line reflections on cables or long PCB traces. The MAX 3000A output drive strength is approximately 8-12 mA per pin - adequate for TTL but marginal for long cables. Use a ground-reference trace alongside each clock signal and keep clock traces under 50 mm to avoid skew.
Compliance Information
RoHS non-compliant per Arrow Electronics distributor listing. Use EPM3128ATC144-5N for RoHS-compliant builds. AEC-Q100 not applicable - this part is not automotive-qualified. Reach, halogen-free, and conflict-minerals status not explicitly stated in verified data.
