EPM5128GC - 128-Macrocell MAX 5000 CPLD | Altera | 68-Pin PGA
MPN： EPM5128GC ✗ 停產EPM5128GC 概覽
What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC containing multiple PLD-like macrocell blocks interconnected by a central programmable interconnect matrix. CPLDs sit between small PAL/GAL devices and large FPGAs, offering deterministic pin-to-pin propagation delays, instant-on configuration (no boot flash needed), and high pin-to-gate density for glue-logic, address decoding, bus interface, and state-machine applications.
Key features of the EPM5128GC include 128 macrocells organized in multiple Logic Array Blocks (LABs), 68 user I/O pins on the ceramic PGA package, and Altera's programmable I/O architecture supporting TTL and CMOS interface levels. The device supports user-programmable security bits and is in-system UV-erasable, making it well suited to engineering development environments where design iteration is expected.
The MAX 5000 architecture uses a CMOS EEPROM-based configuration cell, so the device retains its logic pattern with no external boot PROM. The fixed interconnect provides predictable, consistent timing across operating conditions - a key advantage over SRAM-based FPGAs. With 128 macrocells, the EPM5128GC can implement substantial state machines, multi-channel address decoders, or peripheral bus bridges in a single chip.
Typical applications include prototyping and design iteration of glue-logic designs, replacement of multiple discrete PAL/GAL devices, industrial bus-interface bridging (ISA, parallel port, custom), and educational platforms where UV erasure allows multiple programming cycles. The ceramic PGA package also makes the part useful for laboratory test fixtures and reference designs.
When designing with the EPM5128GC, engineers should provide a clean 5V rail and respect the I/O pin count of 68, configure the device using MAX+PLUS II or the legacy Altera programming toolchain, and note that ceramic PGA sockets are required to allow UV erasure. For new designs, designers should consider the modern MAX II/MAX V equivalents in surface-mount packages.
This page synthesizes distributor availability, parametric alternatives from the same MAX family, and practical design notes not found in the original manufacturer datasheet.
直接替換替代品，適用於 EPM5128GC — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EPM5128GC （相同外形與佔位） — 差異在於 Package, Mounting Type, Configuration Memory, Device Type, Usable Gates.
EPM5128GC-1
✅ 直接替換聯絡詢價
查看資料表 →EPM5064JC-1
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM5064JC
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM5064JC-2
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM5032DC-2
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM5128GC 最大額定值與電氣特性
| Family | MAX 5000 |
| Macrocells | 128 |
| Usable Gates | 2,500 |
| User I/Os | 68 |
| Package Type | WPGA (Windowed Ceramic Pin Grid Array) |
| Package Code | WPGA |
| Number of Terminals | 68 |
| Terminal Form | PIN/PEG (through-hole PGA with alignment pegs) |
| Package Shape | Square |
| Temperature Grade | Commercial |
| Supply Voltage (Vcc) | 5 V |
| Process Technology | CMOS, UV-erasable |
| Architecture | EPLD, programmable AND/OR array with fixed OR plane |
| Programmable Security Bit | Yes |
| Configuration Memory | Non-volatile UV-EPROM (windowed ceramic) |
| 安裝類型 | Through-Hole (PGA socket required) |
EPM5128GC 腳位配置
| 腳位 1 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 2 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 3 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 4 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 5 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 6 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 7 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 8 | GND — Ground |
| 腳位 9 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 10 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 11 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 12 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 13 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 14 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 15 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 16 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 17 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 18 | VCC — 5V supply |
| 腳位 19 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 20 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 21 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 22 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 23 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 24 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 25 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 26 | GND — Ground |
| 腳位 27 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 28 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 29 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 30 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 31 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 32 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 33 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 34 | VCC — 5V supply |
| 腳位 35 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 36 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 37 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 38 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 39 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 40 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 41 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 42 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 43 | GND — Ground |
| 腳位 44 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 45 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 46 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 47 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 48 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 49 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 50 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 51 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 52 | VCC — 5V supply |
| 腳位 53 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 54 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 55 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 56 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 57 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 58 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 59 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 60 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 61 | GND — Ground |
| 腳位 62 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 63 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 64 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 65 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 66 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 67 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
| 腳位 68 | I/O — User I/O pin (assigned by MAX+PLUS II design) |
典型應用
EPM5128GC 適用於 6 應用s: Legacy Glue-Logic Consolidation, Address Decoding and Bus Bridging, UV-Erasable Design Prototyping, Industrial Control State Machines, Peripheral Interface Bridging, Avionics and Military Legacy Maintenance.
Legacy Glue-Logic Consolidation
The EPM5128GC consolidates dozens of discrete 74-series TTL and CMOS glue-logic gates into a single 128-macrocell EPLD, simplifying PCB layout and improving noise immunity in long-life industrial control systems. With 68 user I/Os and predictable MAX 5000 propagation delays, the part directly replaces multiple PAL/GAL devices in backplane interface cards where deterministic timing matters more than raw throughput. Designers port legacy AHDL/VHDL code from MAX+PLUS II and program the device via JTAG.
推薦
Address Decoding and Bus Bridging
The EPM5128GC is well suited to multi-channel address decoding on legacy ISA, VME, and proprietary backplane buses, where 128 macrocells can decode several megabytes of address space with sub-nanosecond deterministic delay. Its 5V-tolerant I/Os interface directly with TTL bus transceivers without level shifters, simplifying the BOM. The non-volatile UV-EPROM configuration eliminates boot PROM requirements, an advantage over SRAM-based FPGAs in mission-critical industrial systems.
推薦
UV-Erasable Design Prototyping
The ceramic windowed PGA (WPGA) package is the EPM5128GC's defining feature for prototyping: the quartz window exposes the EPROM array to UV light, allowing the entire 128-macrocell logic pattern to be erased and re-programmed dozens of times during iterative design cycles. This is invaluable in university and engineering-lab environments where iterative verification requires frequent bitstream updates. Production units migrate to one-time-programmable plastic packages for volume deployment.
推薦
Industrial Control State Machines
Factory automation controllers using the EPM5128GC implement complex Mealy and Moore state machines that coordinate conveyor sequencing, robotic arm interlocks, and safety watchdog logic with deterministic sub-25ns propagation delays. The 5V I/O directly drives industrial 24V opto-isolated inputs via resistor networks, while the wide commercial temperature grade covers most factory floor environments. For harsher conditions, designers migrate to MAX II/MAX V industrial-grade equivalents.
推薦
Peripheral Interface Bridging
The EPM5128GC bridges legacy parallel ports, SCSI interfaces, and custom peripheral buses to modern microcontrollers by implementing bus-format converters, FIFO controllers, and DMA handshaking state machines in a single chip. With 68 user I/Os, the device handles 16-bit data buses plus full handshaking without external mux/demux logic. The MAX architecture's fixed interconnect guarantees predictable timing across voltage and temperature corners, simplifying timing closure.
推薦
Avionics and Military Legacy Maintenance
Avionics and military platforms fielded in the 1990s used the EPM5128GC for mission-computer interface logic, and many of those platforms remain in service decades later, requiring authentic replacement parts for scheduled maintenance. The ceramic WPGA package and -55C to +125C military screening variants (EPM5128GM/883B family) make the part uniquely suited to these long-life programs. Distributors specializing in obsolete military components maintain traceable stock for these applications.
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推薦產品摘要
工程參考資料，適用於 EPM5128GC — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EPM5128GC-1 | EPM5064JC-1 | EPM5064JC | EPM5064JC-2 | EPM5032DC-2 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | WPGA-68 (Windowed Ceramic PGA) | WPGA-68 (Windowed Ceramic PGA) - same | WPGA-68 (Windowed Ceramic PGA) - same | WPGA-68 (Windowed Ceramic PGA) - same | WPGA-68 (Windowed Ceramic PGA) - same | WPGA-68 (Windowed Ceramic PGA) - same |
| Macrocells | 128 | 128 (same) | 64 (-50%) | 64 (-50%) | 64 (-50%) | 32 (-75%) |
| Usable Gates | 2,500 | 2,500 | 2,000 | 2,000 | 2,000 | 1,000 |
| User I/Os | 68 | 68 | 68 | 68 | 68 | 68 (lower drive strength) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Speed/Power Grade | Standard | -1 grade (higher speed option) | -1 grade | Standard | -2 grade | -2 grade |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Erasure Method | UV (windowed) | UV (windowed) | UV (windowed) | UV (windowed) | UV (windowed) | UV (windowed) |
主要差異化特點
- Highest-density MAX 5000 device with 128 macrocells (對比EPM5064JC)
- Same WPGA-68 footprint with higher gate count (對比EPM5032DC-2)
- Windowed UV-erasable package for iterative prototyping (對比MAX II EPM240T100C5N (TQFP-100))
設計說明
The EPM5128GC uses a 68-pin ceramic Pin Grid Array (PGA) package that requires a through-hole PGA socket for programming and UV erasure cycles. When laying out the PCB, reserve a socket footprint with adequate clearance around the ceramic body so the UV eraser lamp can reach the quartz window without obstruction. For production runs, migrate to a one-time-programmable (OTP) plastic package such as the MAX 5000 equivalent in PDIP or PLCC to eliminate the socket cost.
Provide a clean 5V supply to the EPM5128GC with a 100nF ceramic bypass capacitor within 5mm of each VCC pin (multiple VCC and GND pins are distributed across the PGA). Add a 10uF tantalum bulk capacitor at the board entry point. The MAX 5000 family draws substantial inrush current during programming; ensure your 5V regulator can source the Icc peak without sagging, which could corrupt the JTAG programming sequence.
Do not rely on the EPM5128GC for new designs; the MAX 5000 family was discontinued by Altera (now Intel) and the part is in obsolescence with limited inventory. For new development, select a MAX II (EPM240T100C5N), MAX V, or MAX 10 CPLD/FPGA which provide more macrocells, surface-mount packaging, lower power, and active toolchain support. EPM5128GC should be reserved for maintenance of legacy equipment originally designed around it.
When interfacing the EPM5128GC with TTL buses at high edge rates, place 33 ohm series damping resistors on outputs that drive more than 4 inches of trace or fan out to multiple loads, to suppress transmission-line ringing. Use a ground plane on layer 2 of the PCB and keep all I/O traces short (< 2 inches where possible) to control crosstalk. The MAX architecture's deterministic timing assumes lumped-load conditions, so loading analysis is part of the timing closure.
合規資訊
Compliance status not confirmed in available datasheets; the EPM5128GC is an obsolete part from the 1990s and predates modern RoHS documentation requirements. The ceramic PGA package historically contains lead-bearing solder, so RoHS compliance is unlikely; verify with the actual part supplier before using in RoHS-restricted designs.
