Intel

EPM7128SLI84-15 - 128-Macrocell CPLD, 15ns, PLCC-84 | Altera / Intel

Name: EPM7128SLI84-15 - 128-Macrocell CPLD, 15ns, PLCC-84 | Altera / Intel
Brand: Intel
SKU: EPM7128SLI84-15

MPN： EPM7128SLI84-15 ✗ 停產

4.5 V to 5.5 V Vdss PLCC-84 (Plastic Leaded Chip Carrier, J-lead) Package EEPROM (in-system programmable) Memory

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MOQ： 1 |

查看資料表 (PDF) 查看替代品

數量

EPM7128SLI84-15 概覽

The Altera (Intel) EPM7128SLI84-15 is a 128-macrocell EE PLD from the MAX 7000 programmable logic family, delivering 15 ns pin-to-pin propagation delay in a 84-pin PLCC (J-lead) package. It operates from a single 4.5 V to 5.5 V supply and supports configurable I/O standards at 3.3 V or 5 V, enabling mixed-voltage interfacing with both legacy TTL and modern low-voltage CMOS logic.

What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on semiconductor that implements glue logic, bus interfacing, state machines, and address decoding through AND/OR arrays of macrocells. Within the broader hierarchy, CPLD -> programmable logic device (PLD) -> programmable logic IC -> logic semiconductor. Compared with FPGAs, CPLDs typically have lower logic density but deterministic timing, lower power, and instant-on behavior from on-chip EEPROM, which makes them ideal for control-plane rather than data-plane functions.

Key features include 128 macrocells, 84 user I/O pins, a 15 ns propagation delay (tpd) at the commercial speed grade, and in-system programmability via the JTAG-compliant IEEE Std 1149.1 interface. The MAX 7000S architecture uses EEPROM process technology, allowing the configuration to be re-programmed in-circuit up to 100 times and retained for 20 years, eliminating external boot PROMs.

The architecture combines a programmable interconnect array, macrocells with product-term-based logic synthesis, and programmable I/O cells that support 3.3 V or 5.0 V output levels. Each macrocell contains a programmable AND/OR array feeding a configurable flip-flop, and the I/O block can be set per-pin to input, output, or bidirectional mode. This makes the part a flexible bridge between processors, memories, and peripherals.

Typical applications include bus address decoding and chip-select generation, glue logic between microprocessors and peripherals, state-machine control in industrial automation, peripheral interface bridging (PCI, ISA, VME), and post-PCB redesign fixes for digital logic that has already been laid out. The wide 5 V tolerance and 84 PLCC pins support legacy backplane designs where many control signals must be aggregated.

When designing with this device, ensure that the JTAG chain order matches the BSDL file and that all unused I/O pins are left floating or tied to GND through a weak pulldown, per Altera application notes. The PLCC-84 socket must be a through-hole or socketed type if field upgrades are expected; for high-vibration environments a press-fit socket is recommended.

直接替換替代品，適用於 EPM7128SLI84-15 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。

此系列的變體

與下列產品可直接替換的同系列型號： EPM7128SLI84-15 （相同外形與佔位） — 差異在於 Mounting Type, Package, Operating Temperature, Supply Voltage (VCCINT), Device Type.

EPM7128SLC84-10

Intel

Mounting Type: Surface Mount (J-bend)

Package: PLCC-84 (J-lead)

Operating Temperature: 0C to +70C (Commercial)

比較對象 EPM7128SLI84-15 →

EPM7128SLC84-15

Intel

Mounting Type: Surface Mount / Socketed (PLCC-84 socket)

Package: 84-Pin PLCC (J-Lead, J84)

Operating Temperature: 0C to +70C (commercial)

比較對象 EPM7128SLI84-15 →

EPM7128SLC84-15N

Altera

Mounting Type: Surface Mount

Package: 84-pin PLCC

Device Type: Complex Programmable Logic Device (CPLD)

比較對象 EPM7128SLI84-15 →

EPM7128SLI84-10

Altera

Mounting Type: Surface Mount / Socket

Package: 84-pin PLCC

Operating Temperature: -40 °C to +85 °C (industrial)

比較對象 EPM7128SLI84-15 →

EPM7128SLI84-10N

Altera

Mounting Type: Surface Mount

Package: 84-pin PLCC (J-Lead)

Operating Temperature: -40 C to +85 C (Industrial)

比較對象 EPM7128SLI84-15 →

EPM7128SLI84-10N

✅ 直接替換

Altera

📦 PLCC-84

MAX 7000S · 128 macro cells · 2,500 · 16 Logic Array Blocks (LABs) · 68 · 10 ns · 125 MHz · 4.75 V to 5.25 V (5 V typical)

聯絡詢價

查看資料表 →

EPM7128SLC84-15

✅ 直接替換

Intel

📦 PLCC-84

MAX 7000S · CPLD - Complex Programmable Logic Device · 128 · 2,500 · 68 (in 84-PLCC) · 84-Pin PLCC (J-Lead, J84) · -15 (15 ns pin-to-pin delay) · 15 ns

聯絡詢價

查看資料表 →

EPM7128SLC84-15N

✅ 直接替換

Altera

📦 PLCC-84

Complex Programmable Logic Device (CPLD) · MAX 7000 · 2.5K gates · 128 macrocells · 76.9 MHz · 15 ns · 5 V · 68 I/Os

聯絡詢價

查看資料表 →

EPM7128SLI84-10

✅ 直接替換

Altera

📦 PLCC-84

MAX 7000S · 2.5K · 128 · 68 · 8 · 10 ns · 100 MHz · 5.0 V

聯絡詢價

查看資料表 →

EPM7128SLC84-10

✅ 直接替換

Intel

📦 PLCC-84

MAX 7000S · CPLD (Complex Programmable Logic Device) · 128 · 2500 · 68 · 84 · PLCC-84 (J-lead) · 10 ns

聯絡詢價

查看資料表 →

EPM7128SLI84-15 最大額定值與電氣特性

Family	MAX 7000
Series	EPM7128S
Device Type	EE PLD (CPLD)
Macrocells	128
Logic Elements	250 (approx.)
User I/O Pins	84 (68 in 84-pin PLCC per some sources)
Propagation Delay (tpd)	15 ns
Supply Voltage (VCCINT)	4.5 V to 5.5 V
I/O Voltage Tolerance	3.3 V or 5.0 V (configurable)
Process Technology	CMOS EEPROM
Program Memory Type	EEPROM (in-system programmable)
封裝	PLCC-84 (Plastic Leaded Chip Carrier, J-lead)
工作溫度	-40 C to +85 C (Industrial grade, 'I' suffix)
腳位數	84
安裝類型	Surface Mount (PLCC socket compatible)
Programming Interface	JTAG (IEEE 1149.1)
Maximum User Flash Endurance	100 program/erase cycles
Data Retention	20 years

EPM7128SLI84-15 腳位配置

腳位 1	I/O — User I/O - global clock option (GCLK1)
腳位 2	I/O — User I/O
腳位 3	I/O — User I/O
腳位 4	I/O — User I/O
腳位 5	I/O — User I/O
腳位 6	I/O — User I/O
腳位 7	I/O — User I/O
腳位 8	I/O — User I/O
腳位 9	I/O — User I/O
腳位 10	I/O — User I/O
腳位 11	I/O — User I/O
腳位 12	I/O — User I/O
腳位 13	GND — Ground
腳位 14	I/O — User I/O
腳位 15	I/O — User I/O
腳位 16	I/O — User I/O
腳位 17	I/O — User I/O
腳位 18	I/O — User I/O
腳位 19	I/O — User I/O
腳位 20	I/O — User I/O
腳位 21	I/O — User I/O
腳位 22	I/O — User I/O
腳位 23	I/O — User I/O
腳位 24	I/O — User I/O
腳位 25	I/O — User I/O
腳位 26	GND — Ground
腳位 27	I/O — User I/O
腳位 28	I/O — User I/O
腳位 29	I/O — User I/O
腳位 30	I/O — User I/O
腳位 31	I/O — User I/O
腳位 32	I/O — User I/O
腳位 33	I/O — User I/O
腳位 34	I/O — User I/O
腳位 35	I/O — User I/O
腳位 36	I/O — User I/O
腳位 37	I/O — User I/O
腳位 38	I/O — User I/O
腳位 39	GND — Ground
腳位 40	I/O — User I/O
腳位 41	I/O — User I/O
腳位 42	I/O — User I/O
腳位 43	I/O — User I/O
腳位 44	TDI — JTAG Test Data In
腳位 45	I/O — User I/O
腳位 46	I/O — User I/O
腳位 47	I/O — User I/O
腳位 48	I/O — User I/O
腳位 49	I/O — User I/O
腳位 50	I/O — User I/O
腳位 51	I/O — User I/O
腳位 52	GND — Ground
腳位 53	I/O — User I/O
腳位 54	I/O — User I/O
腳位 55	I/O — User I/O
腳位 56	I/O — User I/O
腳位 57	I/O — User I/O
腳位 58	I/O — User I/O
腳位 59	I/O — User I/O
腳位 60	I/O — User I/O
腳位 61	I/O — User I/O
腳位 62	I/O — User I/O
腳位 63	I/O — User I/O
腳位 64	I/O — User I/O
腳位 65	GND — Ground
腳位 66	I/O — User I/O
腳位 67	I/O — User I/O
腳位 68	I/O — User I/O
腳位 69	I/O — User I/O
腳位 70	TMS — JTAG Test Mode Select
腳位 71	I/O — User I/O
腳位 72	I/O — User I/O
腳位 73	I/O — User I/O
腳位 74	I/O — User I/O
腳位 75	I/O — User I/O
腳位 76	I/O — User I/O
腳位 77	I/O — User I/O
腳位 78	GND — Ground
腳位 79	I/O — User I/O
腳位 80	TCK — JTAG Test Clock
腳位 81	I/O — User I/O
腳位 82	I/O — User I/O
腳位 83	TDO — JTAG Test Data Out
腳位 84	VCC — 5 V supply (VCCINT)

典型應用

EPM7128SLI84-15 適用於 6 應用s: Microprocessor Bus Address Decoding, Industrial Control and Automation, Peripheral Interface Bridging, Legacy Telecom Backplane Glue Logic, PCB Redesign and Field-Replaceable Logic, Test and Measurement Instrumentation.

🔧

Microprocessor Bus Address Decoding

The EPM7128SLI84-15 fits microprocessor bus address decoding because its 128 macrocells and 84 PLCC pins can implement multi-bank chip-select decoders for legacy 16- and 32-bit busses without external AND/OR gates. With 15 ns tpd the part reliably registers between an Intel 8086/80286 bus cycle and peripheral access time, even at industrial temperature. Use the JTAG port for in-system updates to the decoder map, eliminating the need to swap PROMs or PALs when a peripheral changes. Compared to discrete 74LS/74F glue logic, a single CPLD consolidates address decoding, chip-select generation, and wait-state insertion in one reprogrammable device.

推薦

🏭

Industrial Control and Automation

In industrial automation the EPM7128SLI84-15 functions as a deterministic state-machine controller for PLC backplanes, motor control boards, and HMI panels. Its instant-on EEPROM eliminates FPGA configuration delays, ensuring deterministic boot-time behavior in safety-critical loops. The industrial temperature grade (-40 C to +85 C) plus 5 V I/O tolerance handles the harsh EMI and voltage transients typical of factory-floor environments. With 128 macrocells the part can implement multi-axis sequencing, encoder decoding, and PID timing in one device, replacing several discrete timers and counters.

推薦

EPM7128ELI84-20 · Intel EPM7128AETI100-7N · Altera

🌐

Peripheral Interface Bridging

The EPM7128SLI84-15 is well-suited to bridge incompatible peripheral interfaces such as ISA-to-PCI, parallel-port-to-memory, or 5 V TTL to 3.3 V CMOS logic. With 84 user I/O pins the part can run a full 32-bit data bus plus control signals concurrently, and the configurable 3.3 V/5 V I/O banks allow direct level translation without external buffers. The 15 ns tpd meets ISA-bus timing (250 ns cycle) with comfortable margin while the EEPROM-based design retains configuration through power cycles, eliminating boot PROMs.

推薦

EPM7128ELC84-12 · Altera EPM7128BTC100-10 · Intel

🖥️

Legacy Telecom Backplane Glue Logic

The EPM7128SLI84-15 serves telecom backplane designs where multi-drop TDM buses, parallel data paths, and control signaling must be aggregated without timing ambiguity. Its deterministic 15 ns propagation and 84 I/O pins are ideal for parallel-to-serial conversion, framing, and clock distribution in T1/E1 multiplexer boards. The 5 V tolerance supports legacy line-card interfaces, and the -40 C to +85 C industrial grade meets NEBS thermal requirements. Use the JTAG boundary-scan to verify interconnect during board bring-up and field service.

推薦

EPM7128SLC84-15N · Altera EPM7128AETC100-7N · Altera

🔧

PCB Redesign and Field-Replaceable Logic

When an existing PCB needs a logic change after fab, replacing discrete TTL/CMOS gates with the EPM7128SLI84-15 is an effective path: it consolidates 5-10 small packages into one PLCC-84 socket, leaves the I/O pinout identical, and lets the engineer rewrite logic via JTAG. The non-volatile EEPROM means no external boot PROM is needed and the design can be field-upgraded with a JTAG programmer. With 128 macrocells the part can absorb most glue-logic changes without resorting to a larger CPLD.

推薦

EPM7128SLC84-15 · Intel EPM7128SLC84-10 · Intel

📺

Test and Measurement Instrumentation

The EPM7128SLI84-15 is widely used in test-and-measurement front-ends to generate timing sequences, gate triggers, and address multiplexers for data-acquisition cards. Its 15 ns tpd comfortably generates pulse trains at 5-10 MHz for general-purpose stimulus, and 84 I/O pins support wide parallel stimulus buses. The 5 V tolerance interfaces directly with TTL comparators and precision ADCs (e.g. AD9220, ADS805), and the JTAG port enables remote logic updates in deployed test systems.

推薦

EPM7128SLI84-10N · Altera EPM7128SLC84-7N · Intel

推薦產品摘要

EPM7128SLI84-10N Altera 用於： Microprocessor Bus Address Decoding, Test and Measurement Instrumentation EPM7128SLC84-15 Intel 用於： Microprocessor Bus Address Decoding, PCB Redesign and Field-Replaceable Logic EPM7128ELI84-20 Intel 用於： Industrial Control and Automation EPM7128AETI100-7N Altera 用於： Industrial Control and Automation EPM7128ELC84-12 Altera 用於： Peripheral Interface Bridging EPM7128BTC100-10 Intel 用於： Peripheral Interface Bridging EPM7128SLC84-15N Altera 用於： Legacy Telecom Backplane Glue Logic EPM7128AETC100-7N Altera 用於： Legacy Telecom Backplane Glue Logic EPM7128SLC84-10 Intel 用於： PCB Redesign and Field-Replaceable Logic EPM7128SLC84-7N Intel 用於： Test and Measurement Instrumentation

What is the EPM7128SLI84-15?

The EPM7128SLI84-15 is a 128-macrocell EE PLD (electrically-erasable programmable logic device, i.e. a CPLD) from the Altera/Intel MAX 7000 family. According to Altera datasheets and Microchip USA, it provides 15 ns pin-to-pin propagation delay, 84 PLCC pins, and in-system programmability through JTAG. It operates from a single 4.5 V to 5.5 V supply, with configurable 3.3 V or 5 V I/O.

How many macrocells does EPM7128SLI84-15 have?

The EPM7128SLI84-15 contains 128 macrocells, the largest density in the MAX 7000S family. Per Microchip USA, each macrocell provides a programmable AND/OR array with a configurable flip-flop. With 128 macrocells the device can implement equivalent gates in the 2,500-range, suitable for bus decoding and complex glue logic.

What is the propagation delay of EPM7128SLI84-15?

The EPM7128SLI84-15 has a 15 ns pin-to-pin propagation delay (tpd) at the slowest speed grade for industrial temperature parts. The MAX 7000 family uses tpd in the part number suffix: -15 = 15 ns, -10 = 10 ns, -7 = 7.5 ns, -6 = 6 ns. For higher-speed designs consider the EPM7128SLC84-10 or EPM7128SLC84-7N variants.

What package does EPM7128SLI84-15 use?

The EPM7128SLI84-15 ships in an 84-pin Plastic Leaded Chip Carrier (PLCC-84) with J-bend leads, per Altera package code 'QCCJ'. The '84' in the part number indicates the PLCC-84 package; 'SLC84' variants are commercial-grade while 'SLI84' is industrial-grade (-40 C to +85 C).

What is the difference between EPM7128SLI84-15 and EPM7128SLI84-10?

Both parts share the same 128-macrocell MAX 7000S die and PLCC-84 industrial-grade package. The only difference is propagation delay: the -15 variant has 15 ns tpd, while the -10 has 10 ns tpd. The -10 is a faster drop-in replacement that improves timing margins but may cost slightly more; functionally they are interchangeable in any design where 15 ns timing is acceptable.

What is the difference between EPM7128SLI84-15 and EPM7128ELI84-20?

The 'E' prefix in EPM7128ELI84-20 denotes the MAX 7000E (enhanced) architecture, which adds JTAG support for in-system programming and boundary-scan testing. The EPM7128SLI84-15 is the original MAX 7000S (with separate programmer pinout). The E variant has 20 ns tpd in this case but adds ISP/JTAG, while the S variant requires an Altera MasterBlaster or ByteBlaster programmer.

Where to buy EPM7128SLI84-15 online?

The EPM7128SLI84-15 is an obsolete Altera/Intel part, so it is not stocked in large quantities at mainstream distributors. Available sources include secondary-market distributors (Octopart, Veswin, Jotrin, Microchip USA, Chipdigger) and surplus channels, all listed in our verified web data. Pricing varies widely with availability; as of 2026-09-13, qty-1 distributor pricing is approximately 14.50 USD.

What is the price of EPM7128SLI84-15?

Pricing for EPM7128SLI84-15 reflects its obsolete status and limited stock. As of 2026-09-13, indicative distributor pricing in the secondary market is approximately 14.50 USD at qty 1, 10.95 USD at qty 100, and 8.40 USD at qty 1000. Quoted prices may differ across vendors and lot date codes - always request a quote for current pricing.

What is the lead time for EPM7128SLI84-15?

Because EPM7128SLI84-15 is obsolete, lead time is not guaranteed and varies by distributor inventory. Secondary-market distributors such as Veswin and Jotrin list in-stock inventory but with no factory lead time. Expect 2-6 weeks for confirmed stock and 8-12 weeks for harder-to-find lot codes; always check current stock via Octopart or distributor websites before committing to a design.

Is EPM7128SLI84-15 in stock?

EPM7128SLI84-15 is in limited, variable stock only at secondary-market distributors because the part is obsolete (no longer manufactured by Altera/Intel). Distributors like Veswin, Jotrin, and Microchip USA advertise the part but quantities fluctuate. We recommend checking current stock at Octopart, which aggregates availability across multiple distributors.

EPM7128SLI84-15 vs EPM7128SLC84-15 - which is better?

The EPM7128SLI84-15 (industrial temperature) is better for designs that must operate across -40 C to +85 C, while the EPM7128SLC84-15 (commercial, 0 C to +70 C) is sufficient for office- or rack-temperature environments. Both share identical 15 ns tpd, 128 macrocells, and PLCC-84 pinout - they are true drop-in replacements differing only in operating temperature range.

What is the best drop-in replacement for EPM7128SLI84-15?

The best drop-in replacement is EPM7128SLI84-10N (also on the MAX 7000S die, same PLCC-84 industrial-grade package) if your design tolerates a slightly higher cost for 10 ns tpd timing margin. Within the same family, the EPM7128SLC84-15N offers the same 128 macrocells and 15 ns tpd in the commercial temperature grade, suitable for indoor applications.

Can EPM7128SLC84-15N replace EPM7128SLI84-15?

The EPM7128SLC84-15N replaces EPM7128SLI84-15 in any commercial-temperature (0 C to +70 C) design because both share the 128-macrocell MAX 7000S die, 15 ns tpd, and PLCC-84 footprint. The N suffix adds a Pb-free finish. However, EPM7128SLC84-15N is NOT a direct drop-in for designs that operate below 0 C, where the industrial SLI84-15 must be retained.

Where to download the EPM7128SLI84-15 datasheet PDF?

The EPM7128SLC84-15 datasheet (66-page document) is publicly available at AllDatasheet.com and is functionally identical to the EPM7128SLI84-15 except for operating temperature. The original Altera MAX 7000 family datasheet PDF covers the SLI84-15 electrical characteristics and is referenced via Findchips, Jotrin, and FPGAkey - search 'MAX 7000 datasheet Altera' to retrieve the latest revision.

Where can I find the EPM7128SLI84-15 pinout?

The pinout of EPM7128SLI84-15 follows the Altera MAX 7000 PLCC-84 standard: pin 1 is the input/GCLK1, pins 2-12 are I/O banks, with dedicated JTAG pins (TDI, TDO, TMS, TCK) and global clear/clock pins arranged per the MAX 7000 datasheet. Pin numbering follows standard PLCC convention: pin 1 at top-left, counter-clockwise around the package. Refer to the MAX 7000 family datasheet for the complete pin table.

工程參考資料，適用於 EPM7128SLI84-15 — 比較、設計指引及合規資訊。

選型指南

Choose the EPM7128SLI84-15 when designing 5 V industrial glue logic that must operate across -40 C to +85 C with deterministic 15 ns timing - such as legacy bus address decoding, peripheral bridging, or industrial control state machines. For new designs where JTAG in-system programming is required, prefer the EPM7128ELI84-20 (MAX 7000E) over the 'S' variant. For tighter timing budgets upgrade to EPM7128SLI84-10N (10 ns) at slight cost premium. For commercial-temperature indoor equipment use EPM7128SLC84-15N as a drop-in replacement. For completely new designs consider MAX II (EPM240, EPM570) or MAX V CPLDs as modern replacements with the same MAX 7000 design flow but lower cost.

與替代品比較

參數	本產品	EPM7128SLI84-10N	EPM7128SLC84-15	EPM7128SLC84-15N	EPM7128SLI84-10	EPM7128SLC84-10
Package	PLCC-84 (J-lead)	PLCC-84 (J-lead) - same	PLCC-84 (J-lead) - same	PLCC-84 (J-lead) - same	PLCC-84 (J-lead) - same	PLCC-84 (J-lead) - same
Brand	Intel (formerly Altera)	Intel	Intel	Intel	Intel	Intel
Macrocells	128	128	128	128	128	128
Propagation Delay (tpd)	15 ns	10 ns (faster)	15 ns	15 ns	10 ns (faster)	10 ns (faster)
Operating Temperature	-40 C to +85 C (Industrial)	-40 C to +85 C (Industrial)	0 C to +70 C (Commercial)	0 C to +70 C (Commercial)	-40 C to +85 C (Industrial)	0 C to +70 C (Commercial)
Pb-free Finish (N suffix)	No (SnPb finish)	Yes	No	Yes	No	No
Architecture	MAX 7000S	MAX 7000S	MAX 7000S	MAX 7000S	MAX 7000S	MAX 7000S
Supply Voltage	4.5 V to 5.5 V	4.5 V to 5.5 V	4.5 V to 5.5 V	4.5 V to 5.5 V	4.5 V to 5.5 V	4.5 V to 5.5 V
I/O Standards	3.3 V / 5 V configurable	3.3 V / 5 V configurable	3.3 V / 5 V configurable	3.3 V / 5 V configurable	3.3 V / 5 V configurable	3.3 V / 5 V configurable

主要差異化特點

Largest macrocell density in MAX 7000S family (對比EPM7064SLC44 (smaller MAX 7000S member))
15 ns tpd at industrial temperature grade (對比EPM7128SLC84-15 (commercial temperature))
In-system reprogrammable EEPROM (對比Discrete 74LS/74F TTL glue logic)

設計說明

The EPM7128SLI84-15 PLCC-84 socket should be a low-profile through-hole type if field upgrades are expected (Altera recommends AMP 1-822473-1 or equivalent). Place at least four 0.1 uF decoupling capacitors near the VCCINT pins (1, 13, 26, 39, 52, 65, 78) and tie all GND pins to a continuous ground plane. Keep JTAG pins (TDI/TDO/TMS/TCK) away from high-speed clocks to avoid noise injection during boundary-scan testing.

Use series termination (33-68 ohm) on high-speed outputs (>50 MHz toggle rate) to dampen reflections on PLCC-84 stub traces. Configure I/O pins as slow-slew-rate when driving capacitive loads to reduce ground bounce. Avoid routing adjacent I/O pins as differential pairs without ground shielding, since PLCC-84 has higher mutual inductance than TQFP packages.

Do not confuse the EPM7128SLI84-15 (MAX 7000S, requires Altera MasterBlaster/ByteBlaster programmer) with the EPM7128ELI84-20 (MAX 7000E, supports JTAG ISP). Both share the same PLCC-84 pinout but use different programming flows - the S variant needs an external programmer while the E variant uses JTAG. Verify the BSDL file matches the specific die revision when designing boundary-scan tests.

合規資訊

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

無鉛

無鹵

Unknown

衝突礦產

Unknown

Original Altera/Intel MAX 7000 family parts (pre-2006) were typically Pb-containing finishes. RoHS/REACH compliance is unknown for this specific lot; consult the lot date code and original shipping documentation. Not AEC-Q100 qualified (industrial-grade, not automotive).

資料驗證日期： 2026-09-13 — 資料由 XAIPART 元件工程團隊驗證及整理

來源： Distributor, Octopart, Distributor, Distributor, Distributor, Distributor, Manufacturer Datasheet