IAUZ40N10S5N130ATMA1 - 100V 40A N-Ch OptiMOS 5 MOSFET | Infineon
MPN： IAUZ40N10S5N130ATMA1 ✓ 啟用中IAUZ40N10S5N130ATMA1 概覽
A power MOSFET is a voltage-controlled semiconductor switch that uses the gate field to modulate conduction between source and drain terminals. N-channel MOSFETs such as the IAUZ40N10S5N130 sit in the hypernym hierarchy discrete semiconductor → transistor → MOSFET → N-channel MOSFET → power MOSFET. Within Infineon's portfolio they belong to the OptiMOS 5 family, which targets high-frequency, low-loss switching in automotive and industrial converters.
Key features include a maximum drain-source voltage V<sub>DS</sub> of 100 V, low gate charge for fast switching, an integrated body diode for inductive commutation, and automotive-grade reliability per AEC-Q101. The PG-TSDSON-8-33 package uses an exposed drain pad for top-side cooling, enabling direct PCB thermal dissipation without an external heatsink at moderate loads. R<sub>DS(on)</sub> at 10 V V<sub>GS</sub> is specified at 13 mΩ maximum per the Infineon product page header.
Technically, the device uses Infineon's latest-generation OptiMOS 5 super-junction trench technology, which achieves the lowest R<sub>DS(on)</sub> × Q<sub>g</sub> figure of merit in its voltage class. The result is reduced switching losses in high-frequency DC-DC converters and motor-drive half-bridges, plus lower conduction losses in synchronous rectification. This translates directly into higher system efficiency and smaller magnetics in switched-mode power supplies.
Typical applications include automotive 48 V mild-hybrid DC-DC converters, LED lighting drivers, motor control and powertrain systems, synchronous rectification in telecom and server SMPS, and battery protection circuits in e-mobility. It is also widely used in industrial solar optimizers and high-current USB-PD sinks. Designers choose it where a 100 V rating margin and AEC-Q101 reliability are needed in a tiny 3.3 × 3.3 mm footprint.
When laying out the PCB, place the source-sense Kelvin connection directly to the package source pad, keep the gate-loop area under 1 cm² to minimize ringing, and use 4-layer FR-4 with at least 2 oz copper on the top layer to spread heat from the exposed drain pad. At 68 W dissipation into a properly designed thermal land pattern, the device can sustain continuous operation without forced airflow.
This page synthesizes distributor pricing, drop-in OptiMOS 5 alternatives, and practical layout guidance not collected in any single datasheet page, enabling faster design-in decisions for automotive and industrial power engineers.
直接替換替代品，適用於 IAUZ40N10S5N130ATMA1 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： IAUZ40N10S5N130ATMA1 （相同外形與佔位） — 差異在於 Package, Technology, Operating Temperature Range, Automotive Qualification, Series.
IAUZ40N10S5N130
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
IAUZ30N10S5L240ATMA1
✅ 直接替換聯絡詢價
查看資料表 →IAUZ40N08S5N100ATMA1
✅ 直接替換聯絡詢價
查看資料表 →IAUZ30N08S5N186ATMA1
✅ 直接替換聯絡詢價
查看資料表 →IAUCN08S7N024ATMA1
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →IAUC100N04S6N028ATMA1
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →IPD068N10N3GATMA1
✅ 直接替換聯絡詢價
查看資料表 →IAUZ40N10S5N130ATMA1 最大額定值與電氣特性
| Manufacturer | Infineon Technologies |
| Part Number | IAUZ40N10S5N130ATMA1 |
| Technology | OptiMOS 5 (super-junction trench) |
| 電晶體類型 | N-Channel MOSFET |
| Drain-Source Voltage (VDS) | 100 V |
| Continuous Drain Current (ID) at Tc=25°C | 40 A |
| Pulsed Drain Current (IDM) | 160 A |
| RDS(on) max at VGS=10V | 13 mΩ |
| RDS(on) typical | 10 mΩ |
| Maximum Power Dissipation (Tc) | 68 W |
| 封裝 | PG-TSDSON-8-33 (S3O8), 3.3 × 3.3 mm |
| 安裝類型 | Surface Mount |
| 工作溫度範圍 | -55°C to +175°C (TJ) |
| Automotive Qualification | AEC-Q101 qualified |
| Lead-Free / RoHS | ROHS3 Compliant |
IAUZ40N10S5N130ATMA1 腳位配置
| 腳位 1 | GATE — Gate drive input; Kelvin source sense for low-inductance gate loop |
| 腳位 2 | SOURCE — Source connection (low-side return) |
| 腳位 3 | SOURCE — Source connection (low-side return) |
| 腳位 4 | SOURCE — Source connection (low-side return) |
| 腳位 5 | NC — Not connected (per datasheet) |
| 腳位 6 | NC — Not connected (per datasheet) |
| 腳位 7 | SOURCE — Source connection (low-side return) |
| 腳位 8 | DRAIN — Drain connection via exposed pad (top-side thermal pad on package bottom) |
安全工作區 (estimated)
典型應用
IAUZ40N10S5N130ATMA1 適用於 7 應用s: 48V Mild-Hybrid Automotive DC-DC Converter, Automotive LED Lighting Drivers, Synchronous Rectification in SMPS, BLDC Motor Drive Half-Bridge, Solar Microinverter / Power Optimizer, Battery Protection & Hot-Swap, USB-PD High-Current Sink.
48V Mild-Hybrid Automotive DC-DC Converter
The IAUZ40N10S5N130ATMA1 is well suited for 48 V mild-hybrid DC-DC converter primary and secondary-side switches, where its 100 V V<sub>DS</sub> rating provides >2x transient margin above the 48 V nominal bus and its 13 mΩ max R<sub>DS(on)</sub> minimizes conduction loss in high-current 1-2 kW power stages. Placed in a half-bridge or synchronous buck topology with 100-200 kHz switching frequency, the OptiMOS 5 die's low Q<sub>g</sub> reduces driver losses and enables smaller magnetics. AEC-Q101 qualification supports ASIL-B system integration for safety-relevant powertrain ECUs, and the 3.3 × 3.3 mm PG-TSDSON-8-33 package saves board area versus D2PAK alternatives.
推薦
Automotive LED Lighting Drivers
In automotive LED headlamp and daytime-running-light driver stages, the IAUZ40N10S5N130ATMA1 serves as the high-side or low-side switch in buck/boost LED current regulators. Its 40 A continuous current comfortably drives multi-LED strings up to 5-10 A per channel, and its 10 mΩ typical R<sub>DS(on)</sub> keeps conduction loss under 1 W at full load, eliminating the need for an external heatsink on the lighting PCB. AEC-Q101 qualification meets automotive headlamp reliability targets, and the small PG-TSDSON-8-33 footprint enables compact driver layouts inside headlamp housings where thermal headroom is constrained.
推薦
Synchronous Rectification in SMPS
The IAUZ40N10S5N130ATMA1 functions as the synchronous rectifier MOSFET in 48 V-input telecom, server, and industrial SMPS, replacing Schottky diodes to gain 1-3% system efficiency. At 100 V V<sub>DS</sub> it handles 48 V nominal with adequate transient margin for telecom battery plants, and its 13 mΩ on-resistance minimizes rectifier conduction loss at 20-30 A output currents. The OptiMOS 5 technology provides an excellent R<sub>DS(on)</sub> × Q<sub>g</sub> figure of merit, allowing high-frequency (200-500 kHz) operation without sacrificing efficiency, which directly reduces magnetic component size.
推薦
BLDC Motor Drive Half-Bridge
In 48 V brushless-DC (BLDC) motor drives for electric power-steering, water pumps, and HVAC blowers, the IAUZ40N10S5N130ATMA1 is deployed as the low-side switch in a three-phase inverter. Its 40 A continuous and 160 A pulsed ratings handle motor inrush and reverse-recovery transients, while the 10 mΩ typical R<sub>DS(on)</sub> reduces I²R heating that would otherwise demand active cooling. The compact PG-TSDSON-8-33 package lets the inverter fit inside the motor housing or ECU, and AEC-Q101 qualification is essential for automotive motor-control safety standards.
推薦
Solar Microinverter / Power Optimizer
In residential solar microinverters and DC power optimizers, the IAUZ40N10S5N130ATMA1 serves as the high-frequency primary switch in isolated or non-isolated DC-DC stages. Its 100 V V<sub>DS</sub> rating suits 60 V<sub>oc</sub> PV panel maximum power points with >1.5x safety margin against cold-panel open-circuit transients, and its low Q<sub>g</sub> supports 100-300 kHz operation that reduces transformer and inductor size. The OptiMOS 5 efficiency gain over older MOSFET generations directly improves CEC-weighted inverter efficiency by 0.3-0.5%, which materially affects solar energy yield over the system's 25-year lifetime.
推薦
Battery Protection & Hot-Swap
In 48 V battery protection circuits, hot-swap controllers, and e-fuse designs, the IAUZ40N10S5N130ATMA1 acts as the main disconnect / current-limit switch. Its 13 mΩ R<sub>DS(on)</sub> keeps the path loss under 50 mV at 40 A load, preserving system efficiency during normal operation, while its 160 A pulsed rating handles inrush transients during hot-plug events. The PG-TSDSON-8-33 package is footprint-compatible with standard hot-swap reference designs, simplifying layout migration from older D2PAK or SO-8 parts.
推薦
USB-PD High-Current Sink
In 100 W-class USB Power Delivery sink designs, the IAUZ40N10S5N130ATMA1 is used as the protection / hot-swap switch on the 20 V input rail from a Type-C connector. Its 100 V rating easily handles 28 V PD EPR (Extended Power Range) transients with significant margin, and its 13 mΩ on-resistance introduces less than 50 mV drop at 5 A continuous load. The PG-TSDSON-8-33 package footprint is small enough to fit inside a laptop docking station's tight board area while dissipating 5-8 W without forced cooling.
推薦
推薦產品摘要
工程參考資料，適用於 IAUZ40N10S5N130ATMA1 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | IAUZ40N10S5N130 | IAUZ30N10S5L240ATMA1 | IAUZ40N08S5N100ATMA1 | IAUZ30N08S5N186ATMA1 | IPD068N10N3GATMA1 |
|---|---|---|---|---|---|---|
| Brand | Infineon | Infineon | Infineon | Infineon | Infineon | Infineon |
| Package | PG-TSDSON-8-33 | PG-TSDSON-8-33 - same | PG-TSDSON-8-33 - same | PG-TSDSON-8-33 - same | PG-TSDSON-8-33 - same | PG-TSDSON-8 - same |
| Drain-Source Voltage (VDS) | 100 V | 100 V | 100 V | 80 V | 80 V | 100 V |
| RDS(on) max @ VGS=10V | 13 mΩ | 13 mΩ | 24 mΩ | 10 mΩ | 18.6 mΩ | 6.8 mΩ |
| Technology | OptiMOS 5 | OptiMOS 5 | OptiMOS 5 | OptiMOS 5 | OptiMOS 5 | OptiMOS 3 |
| Automotive Qualification | AEC-Q101 | AEC-Q101 | AEC-Q101 | AEC-Q101 | AEC-Q101 | AEC-Q101 |
主要差異化特點
- Lowest R<sub>DS(on)</sub> in 100V / 3.3×3.3mm class (對比IAUZ30N10S5L240ATMA1)
- Higher voltage rating than the 80V family (對比IAUZ40N08S5N100ATMA1)
- Newer OptiMOS 5 generation vs OptiMOS 3 (對比IPD068N10N3GATMA1)
- 40 A current vs IAUZ18N10S5L420ATMA1 (對比IAUZ18N10S5L420ATMA1)
設計說明
Estimated: at 68 W maximum dissipation and a typical PG-TSDSON-8-33 RθJA near 50 °C/W on a 4-layer 2-oz FR-4 board, junction temperature rise is roughly 50 °C above ambient at full DC load. The exposed drain pad must be soldered to at least 25 mm² of continuous top-side copper to maintain thermal headroom, with thermal vias to inner copper planes for additional spreading. For continuous operation at currents above 25 A, design the copper area around the package to keep junction-to-ambient below 100 °C.
Keep the gate-drive loop area under 1 cm² by routing the gate trace directly over the drain copper, and place the gate-driver IC adjacent to the gate pin to minimize parasitic inductance. Use a 10 Ω gate-source resistor and a small gate-driver pull-up to prevent false turn-on from drain-voltage transients. Kelvin source connection is provided by dedicated source pins; do not use the exposed drain pad as the only ground return path.
Do not exceed VGS = ±20 V absolute maximum; OptiMOS 5 gate oxide is sensitive to overvoltage and ESD. Add a 10 kΩ gate pull-down to guarantee the FET stays off during controller power-up. The R<sub>DS(on)</sub> specification is given at VGS = 10 V; driving at 4.5 V (logic-level) will increase on-resistance by 50-100%, and at 6 V by 20-30%. Use a true 10 V gate drive for full rated performance.
Recommended land pattern follows JEDEC MO-240 with the central thermal pad at 2.0 × 2.0 mm minimum. Use NSMD (non-solder-mask-defined) pads on the source leads to control solder joint thickness and improve thermal-cycle reliability. A 4-layer stack-up with 2 oz top copper for the drain thermal pad and 1 oz inner planes is recommended for automotive applications targeting 1000+ thermal cycles per AEC-Q101.
合規資訊
ROHS3 compliant per DigiKey product listing. AEC-Q101 qualified (automotive standard), not AEC-Q100. Lead-free reflow-compatible per JEDEC J-STD-020.
