EPM3256ATI144-10 - MAX 3000A 256-Macrocell 10ns CPLD | Intel
MPN: EPM3256ATI144-10 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
Drop-in alternatives for EPM3256ATI144-10 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM3256ATC144-10N
✅ Drop-In✓ In Stock
$14.5 / Unit
View Datasheet →EPM3256ATC144-10AA
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$11.6 / Unit
View Datasheet →EPM3256ATC144-10
✅ Drop-In✓ In Stock
$9.75 / Unit
View Datasheet →EPM3256ATC144-7N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$17.2 / Unit
View Datasheet →EPM3256ATC144-7
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$17.06 / Unit
View Datasheet →EPM3128ATI144-10N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$10.32 / Unit
View Datasheet →EPM3256ATI144-10 Maximum Ratings & Electrical Characteristics
| Series | MAX 3000A |
| Programmable Type | In-System Programmable (ISP), EEPROM-based |
| Number of Macrocells | 256 |
| Number of Logic Elements / Blocks | 16 LABs (Logic Array Blocks) |
| Number of Gates | 5,000 typical usable gates |
| Number of User I/O | 116 |
| Propagation Delay (tpd max) | 10 ns |
| Maximum Frequency (fmax) | 95.2 MHz |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) |
| I/O Voltage Support | MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V mixed |
| Logic Family | CMOS, EEPROM-based |
| Operating Temperature | -40°C to +85°C (industrial) |
| Package | 144-pin TQFP (20x20 mm) |
| Mounting Type | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) and IEEE Std. 1532 ISP |
| Compliance | IEEE Std. 1532 ISP, PCI-compatible I/O |
| Lifecycle Status | Obsolete (per HighqualityPCB listing) |
EPM3256ATI144-10 Pin Configuration
| Pin 1 | I/O — User I/O pin (Bank 1) |
| Pin 2 | I/O — User I/O pin (Bank 1) |
| Pin 3 | I/O — User I/O pin (Bank 1) |
| Pin 4 | I/O — User I/O pin (Bank 1) |
| Pin 5 | I/O — User I/O pin (Bank 1) |
| Pin 6 | I/O — User I/O pin (Bank 1) |
| Pin 7 | I/O — User I/O pin (Bank 1) |
| Pin 8 | I/O — User I/O pin (Bank 1) |
| Pin 9 | I/O — User I/O pin (Bank 1) |
| Pin 10 | I/O — User I/O pin (Bank 1) |
| Pin 11 | I/O — User I/O pin (Bank 1) |
| Pin 12 | I/O — User I/O pin (Bank 1) |
| Pin 13 | I/O — User I/O pin (Bank 2) |
| Pin 14 | I/O — User I/O pin (Bank 2) |
| Pin 15 | I/O — User I/O pin (Bank 2) |
| Pin 16 | I/O — User I/O pin (Bank 2) |
| Pin 17 | I/O — User I/O pin (Bank 2) |
| Pin 18 | I/O — User I/O pin (Bank 2) |
| Pin 19 | I/O — User I/O pin (Bank 2) |
| Pin 20 | I/O — User I/O pin (Bank 2) |
| Pin 21 | GND — Ground |
| Pin 22 | I/O — User I/O pin (Bank 2) |
| Pin 23 | I/O — User I/O pin (Bank 2) |
| Pin 24 | I/O — User I/O pin (Bank 2) |
| Pin 25 | I/O — User I/O pin (Bank 2) |
| Pin 26 | I/O — User I/O pin (Bank 2) |
| Pin 27 | I/O — User I/O pin (Bank 2) |
| Pin 28 | I/O — User I/O pin (Bank 2) |
| Pin 29 | I/O — User I/O pin (Bank 2) |
| Pin 30 | I/O — User I/O pin (Bank 2) |
| Pin 31 | GND — Ground |
| Pin 32 | I/O — User I/O pin (Bank 2) |
| Pin 33 | I/O — User I/O pin (Bank 3) |
| Pin 34 | I/O — User I/O pin (Bank 3) |
| Pin 35 | I/O — User I/O pin (Bank 3) |
| Pin 36 | I/O — User I/O pin (Bank 3) |
| Pin 37 | I/O — User I/O pin (Bank 3) |
| Pin 38 | I/O — User I/O pin (Bank 3) |
| Pin 39 | I/O — User I/O pin (Bank 3) |
| Pin 40 | I/O — User I/O pin (Bank 3) |
| Pin 41 | I/O — User I/O pin (Bank 3) |
| Pin 42 | I/O — User I/O pin (Bank 3) |
| Pin 43 | GND — Ground |
| Pin 44 | I/O — User I/O pin (Bank 3) |
| Pin 45 | I/O — User I/O pin (Bank 3) |
| Pin 46 | I/O — User I/O pin (Bank 3) |
| Pin 47 | I/O — User I/O pin (Bank 3) |
| Pin 48 | I/O — User I/O pin (Bank 3) |
| Pin 49 | I/O — User I/O pin (Bank 3) |
| Pin 50 | I/O — User I/O pin (Bank 3) |
| Pin 51 | I/O — User I/O pin (Bank 3) |
| Pin 52 | I/O — User I/O pin (Bank 3) |
| Pin 53 | I/O — User I/O pin (Bank 3) |
| Pin 54 | I/O — User I/O pin (Bank 3) |
| Pin 55 | I/O — User I/O pin (Bank 4) |
| Pin 56 | I/O — User I/O pin (Bank 4) |
| Pin 57 | I/O — User I/O pin (Bank 4) |
| Pin 58 | I/O — User I/O pin (Bank 4) |
| Pin 59 | I/O — User I/O pin (Bank 4) |
| Pin 60 | I/O — User I/O pin (Bank 4) |
| Pin 61 | GND — Ground |
| Pin 62 | I/O — User I/O pin (Bank 4) |
| Pin 63 | I/O — User I/O pin (Bank 4) |
| Pin 64 | I/O — User I/O pin (Bank 4) |
| Pin 65 | I/O — User I/O pin (Bank 4) |
| Pin 66 | I/O — User I/O pin (Bank 4) |
| Pin 67 | I/O — User I/O pin (Bank 4) |
| Pin 68 | I/O — User I/O pin (Bank 4) |
| Pin 69 | I/O — User I/O pin (Bank 4) |
| Pin 70 | I/O — User I/O pin (Bank 4) |
| Pin 71 | I/O — User I/O pin (Bank 4) |
| Pin 72 | I/O — User I/O pin (Bank 4) |
| Pin 73 | TDI — JTAG Test Data In (IEEE 1149.1) |
| Pin 74 | TMS — JTAG Test Mode Select |
| Pin 75 | TCK — JTAG Test Clock |
| Pin 76 | GND — Ground |
| Pin 77 | VCCINT — Core supply 3.3 V (3.0-3.6 V) |
| Pin 78 | I/O — User I/O pin (Bank 4) |
| Pin 79 | I/O — User I/O pin (Bank 4) |
| Pin 80 | I/O — User I/O pin (Bank 4) |
| Pin 81 | I/O — User I/O pin (Bank 4) |
| Pin 82 | I/O — User I/O pin (Bank 1) |
| Pin 83 | I/O — User I/O pin (Bank 1) |
| Pin 84 | I/O — User I/O pin (Bank 1) |
| Pin 85 | I/O — User I/O pin (Bank 1) |
| Pin 86 | I/O — User I/O pin (Bank 1) |
| Pin 87 | I/O — User I/O pin (Bank 1) |
| Pin 88 | I/O — User I/O pin (Bank 1) |
| Pin 89 | I/O — User I/O pin (Bank 1) |
| Pin 90 | I/O — User I/O pin (Bank 1) |
| Pin 91 | GND — Ground |
| Pin 92 | I/O — User I/O pin (Bank 1) |
| Pin 93 | I/O — User I/O pin (Bank 1) |
| Pin 94 | I/O — User I/O pin (Bank 1) |
| Pin 95 | I/O — User I/O pin (Bank 1) |
| Pin 96 | I/O — User I/O pin (Bank 1) |
| Pin 97 | I/O — User I/O pin (Bank 1) |
| Pin 98 | I/O — User I/O pin (Bank 1) |
| Pin 99 | I/O — User I/O pin (Bank 1) |
| Pin 100 | I/O — User I/O pin (Bank 1) |
| Pin 101 | I/O — User I/O pin (Bank 1) |
| Pin 102 | I/O — User I/O pin (Bank 2) |
| Pin 103 | I/O — User I/O pin (Bank 2) |
| Pin 104 | I/O — User I/O pin (Bank 2) |
| Pin 105 | I/O — User I/O pin (Bank 2) |
| Pin 106 | I/O — User I/O pin (Bank 2) |
| Pin 107 | GND — Ground |
| Pin 108 | I/O — User I/O pin (Bank 2) |
| Pin 109 | I/O — User I/O pin (Bank 2) |
| Pin 110 | I/O — User I/O pin (Bank 2) |
| Pin 111 | I/O — User I/O pin (Bank 2) |
| Pin 112 | I/O — User I/O pin (Bank 2) |
| Pin 113 | I/O — User I/O pin (Bank 2) |
| Pin 114 | I/O — User I/O pin (Bank 2) |
| Pin 115 | I/O — User I/O pin (Bank 3) |
| Pin 116 | I/O — User I/O pin (Bank 3) |
| Pin 117 | I/O — User I/O pin (Bank 3) |
| Pin 118 | I/O — User I/O pin (Bank 3) |
| Pin 119 | GND — Ground |
| Pin 120 | I/O — User I/O pin (Bank 3) |
| Pin 121 | I/O — User I/O pin (Bank 3) |
| Pin 122 | I/O — User I/O pin (Bank 3) |
| Pin 123 | I/O — User I/O pin (Bank 3) |
| Pin 124 | I/O — User I/O pin (Bank 3) |
| Pin 125 | I/O — User I/O pin (Bank 3) |
| Pin 126 | I/O — User I/O pin (Bank 3) |
| Pin 127 | I/O — User I/O pin (Bank 4) |
| Pin 128 | I/O — User I/O pin (Bank 4) |
| Pin 129 | I/O — User I/O pin (Bank 4) |
| Pin 130 | I/O — User I/O pin (Bank 4) |
| Pin 131 | I/O — User I/O pin (Bank 4) |
| Pin 132 | GND — Ground |
| Pin 133 | I/O — User I/O pin (Bank 4) |
| Pin 134 | I/O — User I/O pin (Bank 4) |
| Pin 135 | VCCIO — I/O bank supply voltage |
| Pin 136 | VCCIO — I/O bank supply voltage |
| Pin 137 | VCCINT — Core supply 3.3 V |
| Pin 138 | TDO — JTAG Test Data Out |
| Pin 139 | GND — Ground |
| Pin 140 | I/O — User I/O pin (Bank 4) |
| Pin 141 | I/O — User I/O pin (Bank 4) |
| Pin 142 | I/O — User I/O pin (Bank 4) |
| Pin 143 | I/O — User I/O pin (Bank 4) |
| Pin 144 | I/O — User I/O pin (Bank 4) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3256ATI144-10 is suitable for 6 applications: Microcontroller Bus-Interface Glue Logic, Address Decoding and Chip-Select Generation, Peripheral Controllers (UART/SPI/I2C Bridges), State Machine and Sequencer Controllers, PCI Add-in Card Auxiliary Logic, Legacy System Sustainment and Last-Time-Buy.
Microcontroller Bus-Interface Glue Logic
The EPM3256ATI144-10 fits microcontroller bus-interface bridge designs where 256 macrocells and 116 user I/Os are needed to consolidate scattered 74-series logic into a single non-volatile device. With 10 ns tpd and 95.2 MHz fmax it comfortably bridges 33 MHz address/data buses. Its instant-on EEPROM eliminates FPGA boot delays on power-up, ensuring deterministic bus arbitration at reset. Pin count supports wide 32-bit data plus 24-bit address plus control signal decoding on a single device.
Recommended
Address Decoding and Chip-Select Generation
The 256 macrocells of the EPM3256ATI144-10 support wide address decoding trees for memory-mapped systems with up to 32-bit address buses, generating dozens of chip-select signals with predictable combinational delay. MultiVolt I/O (1.8/2.5/3.3/5.0 V) lets a single CPLD interface modern 1.8 V memory controllers and legacy 5 V peripherals without external level shifters. JTAG ISP allows last-minute CS map updates during board bring-up.
Recommended
Peripheral Controllers (UART/SPI/I2C Bridges)
Industrial control boards use the EPM3256ATI144-10 to implement multi-channel UART, SPI, and I2C controllers with hardware state machines rather than firmware bit-banging. The 116 user I/Os support up to a dozen full-duplex serial channels, and the deterministic 10 ns tpd simplifies worst-case latency analysis. Industrial -40 to +85°C operation suits factory floor equipment. JTAG boundary-scan plus ISP simplifies field firmware upgrades via the IEEE Std. 1532 flow.
Recommended
State Machine and Sequencer Controllers
The MAX 3000A architecture is optimized for finite state machines (FSMs) and sequencers, making the EPM3256ATI144-10 ideal for motor-control sequencers, instrumentation state machines, and protocol sequencers. Each of the 256 macrocells holds a registered state bit, supporting FSMs with up to 32 states without logic splitting. EEPROM configuration guarantees deterministic startup, critical for safety sequencing where FPGA boot is unacceptable.
Recommended
PCI Add-in Card Auxiliary Logic
The PCI-compatible I/O drivers and 3.3V/5V-tolerant MultiVolt interface make the EPM3256ATI144-10 a traditional choice for legacy PCI add-in cards requiring auxiliary glue logic, EEPROM emulation, or local bus decoding. The 116 I/Os accommodate PCI 32-bit data/address plus auxiliary GPIO. Industrial temperature supports outdoor PCI instrumentation. Designers should pair with PCI bridge ASICs and verify against PCI Local Bus Specification 2.2 timing.
Recommended
Legacy System Sustainment and Last-Time-Buy
Many industrial and aerospace programs continue to use the EPM3256ATI144-10 in long-lifecycle systems (factory controllers, medical instrumentation, military-grade boards) where redesign is cost-prohibitive. The industrial -40 to +85°C range and EEPROM-based non-volatile configuration suit 15 to 20 year field deployments. Sustainment teams should secure last-time-buy inventory, identify pin-compatible MAX 3000A variants (EPM3256ATC144-10N) for cross-stock, and qualify modern MAX II replacements where PCB rework is feasible.
Recommended
Recommended Products Summary
Engineering reference data for EPM3256ATI144-10 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3256ATC144-10N | EPM3256ATC144-10AA | EPM3256ATC144-10 | EPM3256ATC144-7N | EPM3128ATI144-10N |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | 144-TQFP (20x20 mm) | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same |
| Number of Macrocells | 256 | 256 | 256 | 256 | 256 | 128 (-50%) |
| Propagation Delay (tpd max) | 10 ns | 10 ns | 10 ns | 10 ns | 7.5 ns (faster) | 10 ns |
| Operating Temperature | -40°C to +85°C (industrial) | 0°C to +70°C (commercial) | 0°C to +70°C (commercial) | 0°C to +70°C (commercial) | 0°C to +70°C (commercial) | -40°C to +85°C (industrial) |
| User I/Os | 116 | 116 | 116 | 116 | 116 | 96 |
| VCCINT Supply | 3.0 to 3.6 V (3.3 V nom) | 3.0 to 3.6 V | 3.0 to 3.6 V | 3.0 to 3.6 V | 3.0 to 3.6 V | 3.0 to 3.6 V |
| Series | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature range (-40°C to +85°C) (vs EPM3256ATC144-10N)
- Highest macrocell count in the 144-TQFP MAX 3000A family (vs EPM3128ATI144-10N)
- 10 ns propagation delay with full I/O count (vs EPM3256ATC144-7N)
Design Notes
The EPM3256ATI144-10 operates from a single 3.3 V VCCINT supply (3.0 to 3.6 V). Decouple VCCINT and each VCCIO bank with 0.1 µF ceramic capacitors placed within 5 mm of each supply pin, plus a bulk 10 µF tantalum per bank. MultiVolt I/O banks must each have their own VCCIO rail (1.8/2.5/3.3/5.0 V) — do not tie VCCIO banks together if your design uses mixed voltages. IccINT during ISP programming is approximately 50% higher than in user mode; ensure regulator headroom.
The 144-TQFP (20x20 mm) has 0.5 mm pitch leads — use 0.15 mm trace/space design rules with 0.25 mm via drill minimum. Provide a solid ground pour under the device for thermal spreading and signal-integrity. Place JTAG header or test points for TDI/TDO/TMS/TCK near the board edge to simplify ISP programming and boundary-scan test. Add 10 kΩ pull-ups on TDI, TMS, and TCK per IEEE 1149.1 to keep the JTAG TAP controller in known state at power-up.
Do not use I/O pins before JTAG programming finishes — leaving pins floating during ISP can cause bus contention. For unused I/O pins, configure them as outputs driving low (not high-Z) in the Quartus II pin assignment. Do not exceed 24 mA sink current per I/O (per the MAX 3000A datasheet recommendation). For new designs, migrate to MAX II (EPM240T144C5N) or MAX V (5M240ZT100C5N) families — they offer more logic density, lower power, and active production status.
Compliance Information
Compliance information not present in verified web data. EPM3256ATI144-10 is an obsolete CPLD; RoHS status for this specific part was not found in DigiKey/Mouser/Octopart listings. Check Intel/legacy Altera documentation for original compliance declarations.
