EPM9560RZ208-15 - MAX 9000 EPLD, 560 Logic Elements | Altera
料号： EPM9560RZ208-15 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $85 | $85.00 |
| 10 | $76.5 | $765.00 |
| 100 | $68 | $6,800.00 |
| 500 | $61.2 | $30,600.00 |
| 1,000 | $55 | $55,000.00 |
EPM9560RZ208-15 概述
An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with multi-macrocell arrays, in-system programmability via IEEE 1149.1 JTAG, and predictable timing. In the broader taxonomy, an EPLD is a sub-class of CPLD (Complex Programmable Logic Device), which itself sits between discrete PLDs and high-density FPGAs. MAX 9000 sits near the upper end of the CPLD density envelope offered in the late-1990s/early-2000s Altera portfolio, providing high I/O counts and predictable timing suitable for board-level glue logic.
Key features include 560 macrocells, 16 logic array blocks (LABs), 212 user I/O pins, 5V tolerant I/O on selected variants, in-system programmability (ISP) through JTAG, and a maximum toggle frequency of 100 MHz. The FastTrack interconnect provides continuous routing that yields fully deterministic, hazard-free timing — every path through the device has a guaranteed propagation delay independent of logic placement. Designers can therefore budget timing without floorplanning iterations.
The RQFP-208 package offers 208 pins with low profile suitable for socketed and surface-mount designs. With 212 user I/Os available in the package and high-drive capability on outputs, the EPM9560RZ208-15 is well suited for parallel bus interfaces, address decoding, memory control, and peripheral multiplexing tasks where multiple discrete 74-series devices would otherwise be required. The -15 speed grade delivers tPD = 15 ns, suiting 33 MHz synchronous designs.
Typical applications include legacy industrial control systems, telecommunications backplane glue logic, ISA/PCI bus address decoding, and microcontroller peripheral expansion. The wide I/O count and predictable timing also suit it for ASIC prototyping in designs that later migrate to structured ASIC or gate-array devices.
When designing with the EPM9560RZ208-15, note that the device is a mature part approaching end-of-life. Designers of new products should consider the Altera (Intel) MAX V, MAX II, or MAX 10 CPLD families, which offer lower power, smaller packages, and modern I/O standards. For legacy board replacement, verify pin compatibility with the original design footprint and review the datasheet's DC characteristics, particularly VCCIO banks and 5V tolerance.
This page synthesizes distributor pricing, drop-in alternatives from the MAX 9000 family, and practical design notes not consolidated in the manufacturer datasheet — giving sourcing engineers a single reference for both qualification and substitution decisions.
直接替换替代料： EPM9560RZ208-15 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM9560RZ208-15 （相同外形与封装尺寸） ——差异在于 Package, Usable Gates, Architecture, Device Type, Configuration Memory.
快速对比工具——选择替代料号进行并排对比：
EPM9560RI208-15
✅ 直接替换✓ 有现货
$20.1 / 个
查看数据手册 →EPM9560RI208-20
✅ 直接替换✓ 有现货
$21.1 / 个
查看数据手册 →EPM9560RI208-10
✅ 直接替换✓ 有现货
$67.8 / 个
查看数据手册 →EPM9560RC208-15
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →EPM9480RC208-15
✅ 直接替换✓ 有现货
$24.95 / 个
查看数据手册 →EPM9400RC208-20
✅ 直接替换✓ 有现货
$60.49 / 个
查看数据手册 →EPM9560RZ208-15 最大额定值与电气特性
| Family | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks (LABs) | 16 |
| User I/O Pins (max) | 212 |
| 封装 | RQFP-208 (PowerQuad QFP) |
| Speed Grade | -15 (15 ns pin-to-pin delay) |
| Process Technology | 0.35 µm CMOS EEPROM |
| Operating Voltage (Core) | 5.0 V |
| Programmability | In-System Programmable (ISP) via JTAG |
| Pin-to-Pin Delay (tPD) | 15 ns |
| 安装类型 | Surface Mount |
EPM9560RZ208-15 引脚配置
| 引脚 1 | GND — Ground reference (TQFP convention - check datasheet for exact assignment) |
| 引脚 2 | I/O — User I/O pin (function assigned by Quartus design) |
| 引脚 3 | I/O — User I/O pin |
| 引脚 4 | I/O — User I/O pin |
| 引脚 5 | I/O — User I/O pin |
| 引脚 6 | I/O — User I/O pin |
| 引脚 7 | I/O — User I/O pin |
| 引脚 8 | I/O — User I/O pin |
| 引脚 9 | I/O — User I/O pin |
| 引脚 10 | I/O — User I/O pin |
| 引脚 11 | I/O — User I/O pin |
| 引脚 12 | I/O — User I/O pin |
| 引脚 13 | I/O — User I/O pin |
| 引脚 14 | I/O — User I/O pin |
| 引脚 15 | I/O — User I/O pin |
| 引脚 16 | GND — Ground reference |
| 引脚 17 | I/O — User I/O pin |
| 引脚 18 | I/O — User I/O pin |
| 引脚 19 | I/O — User I/O pin |
| 引脚 20 | I/O — User I/O pin |
| 引脚 21 | I/O — User I/O pin |
| 引脚 22 | I/O — User I/O pin |
| 引脚 23 | I/O — User I/O pin |
| 引脚 24 | I/O — User I/O pin |
| 引脚 25 | I/O — User I/O pin |
| 引脚 26 | I/O — User I/O pin |
| 引脚 27 | I/O — User I/O pin |
| 引脚 28 | VCC — +5V core supply |
| 引脚 29 | I/O — User I/O pin |
| 引脚 30 | I/O — User I/O pin |
| 引脚 31 | I/O — User I/O pin |
| 引脚 32 | I/O — User I/O pin |
| 引脚 33 | I/O — User I/O pin |
| 引脚 34 | I/O — User I/O pin |
| 引脚 35 | I/O — User I/O pin |
| 引脚 36 | I/O — User I/O pin |
| 引脚 37 | I/O — User I/O pin |
| 引脚 38 | I/O — User I/O pin |
| 引脚 39 | I/O — User I/O pin |
| 引脚 40 | I/O — User I/O pin |
| 引脚 41 | I/O — User I/O pin |
| 引脚 42 | I/O — User I/O pin |
| 引脚 43 | I/O — User I/O pin |
| 引脚 44 | I/O — User I/O pin |
| 引脚 45 | I/O — User I/O pin |
| 引脚 46 | I/O — User I/O pin |
| 引脚 47 | I/O — User I/O pin |
| 引脚 48 | I/O — User I/O pin |
| 引脚 49 | I/O — User I/O pin |
| 引脚 50 | I/O — User I/O pin |
| 引脚 51 | I/O — User I/O pin |
| 引脚 52 | GND — Ground reference |
| 引脚 53 | I/O — User I/O pin |
| 引脚 54 | I/O — User I/O pin |
| 引脚 55 | I/O — User I/O pin |
| 引脚 56 | I/O — User I/O pin |
| 引脚 57 | I/O — User I/O pin |
| 引脚 58 | I/O — User I/O pin |
| 引脚 59 | I/O — User I/O pin |
| 引脚 60 | I/O — User I/O pin |
| 引脚 61 | I/O — User I/O pin |
| 引脚 62 | I/O — User I/O pin |
| 引脚 63 | I/O — User I/O pin |
| 引脚 64 | I/O — User I/O pin |
| 引脚 65 | I/O — User I/O pin |
| 引脚 66 | I/O — User I/O pin |
| 引脚 67 | I/O — User I/O pin |
| 引脚 68 | I/O — User I/O pin |
| 引脚 69 | I/O — User I/O pin |
| 引脚 70 | I/O — User I/O pin |
| 引脚 71 | I/O — User I/O pin |
| 引脚 72 | I/O — User I/O pin |
| 引脚 73 | I/O — User I/O pin |
| 引脚 74 | I/O — User I/O pin |
| 引脚 75 | I/O — User I/O pin |
| 引脚 76 | I/O — User I/O pin |
| 引脚 77 | TDI — JTAG Test Data In |
| 引脚 78 | TMS — JTAG Test Mode Select |
| 引脚 79 | TCK — JTAG Test Clock |
| 引脚 80 | TDO — JTAG Test Data Out |
| 引脚 81 | I/O — User I/O pin |
| 引脚 82 | I/O — User I/O pin |
| 引脚 83 | I/O — User I/O pin |
| 引脚 84 | I/O — User I/O pin |
| 引脚 85 | I/O — User I/O pin |
| 引脚 86 | I/O — User I/O pin |
| 引脚 87 | I/O — User I/O pin |
| 引脚 88 | GND — Ground reference |
| 引脚 89 | I/O — User I/O pin |
| 引脚 90 | I/O — User I/O pin |
| 引脚 91 | I/O — User I/O pin |
| 引脚 92 | I/O — User I/O pin |
| 引脚 93 | I/O — User I/O pin |
| 引脚 94 | I/O — User I/O pin |
| 引脚 95 | I/O — User I/O pin |
| 引脚 96 | I/O — User I/O pin |
| 引脚 97 | I/O — User I/O pin |
| 引脚 98 | I/O — User I/O pin |
| 引脚 99 | I/O — User I/O pin |
| 引脚 100 | I/O — User I/O pin |
| 引脚 101 | I/O — User I/O pin |
| 引脚 102 | I/O — User I/O pin |
| 引脚 103 | I/O — User I/O pin |
| 引脚 104 | I/O — User I/O pin |
| 引脚 105 | I/O — User I/O pin |
| 引脚 106 | I/O — User I/O pin |
| 引脚 107 | I/O — User I/O pin |
| 引脚 108 | I/O — User I/O pin |
| 引脚 109 | I/O — User I/O pin |
| 引脚 110 | I/O — User I/O pin |
| 引脚 111 | I/O — User I/O pin |
| 引脚 112 | I/O — User I/O pin |
| 引脚 113 | I/O — User I/O pin |
| 引脚 114 | I/O — User I/O pin |
| 引脚 115 | I/O — User I/O pin |
| 引脚 116 | I/O — User I/O pin |
| 引脚 117 | I/O — User I/O pin |
| 引脚 118 | I/O — User I/O pin |
| 引脚 119 | I/O — User I/O pin |
| 引脚 120 | I/O — User I/O pin |
| 引脚 121 | I/O — User I/O pin |
| 引脚 122 | I/O — User I/O pin |
| 引脚 123 | I/O — User I/O pin |
| 引脚 124 | I/O — User I/O pin |
| 引脚 125 | I/O — User I/O pin |
| 引脚 126 | I/O — User I/O pin |
| 引脚 127 | I/O — User I/O pin |
| 引脚 128 | GND — Ground reference |
| 引脚 129 | I/O — User I/O pin |
| 引脚 130 | I/O — User I/O pin |
| 引脚 131 | I/O — User I/O pin |
| 引脚 132 | I/O — User I/O pin |
| 引脚 133 | I/O — User I/O pin |
| 引脚 134 | I/O — User I/O pin |
| 引脚 135 | I/O — User I/O pin |
| 引脚 136 | I/O — User I/O pin |
| 引脚 137 | I/O — User I/O pin |
| 引脚 138 | I/O — User I/O pin |
| 引脚 139 | I/O — User I/O pin |
| 引脚 140 | I/O — User I/O pin |
| 引脚 141 | I/O — User I/O pin |
| 引脚 142 | I/O — User I/O pin |
| 引脚 143 | I/O — User I/O pin |
| 引脚 144 | I/O — User I/O pin |
| 引脚 145 | I/O — User I/O pin |
| 引脚 146 | I/O — User I/O pin |
| 引脚 147 | I/O — User I/O pin |
| 引脚 148 | I/O — User I/O pin |
| 引脚 149 | I/O — User I/O pin |
| 引脚 150 | I/O — User I/O pin |
| 引脚 151 | I/O — User I/O pin |
| 引脚 152 | I/O — User I/O pin |
| 引脚 153 | I/O — User I/O pin |
| 引脚 154 | VCC — +5V core supply |
| 引脚 155 | I/O — User I/O pin |
| 引脚 156 | I/O — User I/O pin |
| 引脚 157 | I/O — User I/O pin |
| 引脚 158 | I/O — User I/O pin |
| 引脚 159 | I/O — User I/O pin |
| 引脚 160 | I/O — User I/O pin |
| 引脚 161 | I/O — User I/O pin |
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| 引脚 171 | I/O — User I/O pin |
| 引脚 172 | I/O — User I/O pin |
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| 引脚 174 | I/O — User I/O pin |
| 引脚 175 | I/O — User I/O pin |
| 引脚 176 | I/O — User I/O pin |
| 引脚 177 | I/O — User I/O pin |
| 引脚 178 | I/O — User I/O pin |
| 引脚 179 | I/O — User I/O pin |
| 引脚 180 | I/O — User I/O pin |
| 引脚 181 | I/O — User I/O pin |
| 引脚 182 | GND — Ground reference |
| 引脚 183 | I/O — User I/O pin |
| 引脚 184 | I/O — User I/O pin |
| 引脚 185 | I/O — User I/O pin |
| 引脚 186 | I/O — User I/O pin |
| 引脚 187 | I/O — User I/O pin |
| 引脚 188 | I/O — User I/O pin |
| 引脚 189 | I/O — User I/O pin |
| 引脚 190 | I/O — User I/O pin |
| 引脚 191 | I/O — User I/O pin |
| 引脚 192 | I/O — User I/O pin |
| 引脚 193 | I/O — User I/O pin |
| 引脚 194 | I/O — User I/O pin |
| 引脚 195 | I/O — User I/O pin |
| 引脚 196 | I/O — User I/O pin |
| 引脚 197 | I/O — User I/O pin |
| 引脚 198 | I/O — User I/O pin |
| 引脚 199 | I/O — User I/O pin |
| 引脚 200 | I/O — User I/O pin |
| 引脚 201 | I/O — User I/O pin |
| 引脚 202 | I/O — User I/O pin |
| 引脚 203 | I/O — User I/O pin |
| 引脚 204 | I/O — User I/O pin |
| 引脚 205 | I/O — User I/O pin |
| 引脚 206 | I/O — User I/O pin |
| 引脚 207 | I/O — User I/O pin |
| 引脚 208 | I/O — User I/O pin |
典型应用
EPM9560RZ208-15 适用于 6 应用s: Legacy Industrial Control Systems, Telecommunications Backplane Glue Logic, ISA/PCI Bus Address Decoding, Microcontroller Peripheral Expansion, ASIC Prototyping and Logic Consolidation, Legacy Board Repair and Last-Time-Buy Stock.
Legacy Industrial Control Systems
The EPM9560RZ208-15 fits legacy industrial control systems because its 560 macrocells and 212 user I/Os can replace dozens of discrete 74-series logic devices on a control board, dramatically reducing component count and improving reliability. The device's 15 ns tPD comfortably supports 33 MHz synchronous operation typical of PLC backplanes, motor-control interfaces, and sensor-multiplexing boards. The RQFP-208 package's surface-mount profile also suits modernized control cabinets where vibration resistance is critical. Compared to a discrete logic implementation, a single MAX 9560 reduces PCB area by 60–80% and simplifies BOM management. The device's non-volatile EEPROM configuration means no external boot PROM is required — power-on behavior is deterministic. This makes the EPM9560RZ208-15 a strong candidate for repairing or extending legacy control systems whose original CPLD has failed or whose logic must be updated to support new sensor types.
推荐
Telecommunications Backplane Glue Logic
The EPM9560RZ208-15 fits telecommunications backplane glue-logic applications because its high I/O count (212 pins) can simultaneously address multiple bus segments, control line interfaces, and timing-synchronization signals on a backplane mid-plane. The deterministic tPD = 15 ns timing enables the device to reliably bridge 33 MHz TDM buses, E1/T1 framers, and HDLC controllers without violating setup/hold budgets. The FastTrack continuous interconnect ensures every signal path has the same delay regardless of placement — a critical property for backplane designs where signal-integrity margins are tight. Compared to FPGA alternatives, the MAX 9560's instant-on (no configuration time) and 5V-tolerant I/Os make it simpler to integrate with legacy line-interface units. The RQFP-208 package supports the high pin density required for backplane glue logic. For TDM and SDH backplanes operating at speeds up to 52 Mbps, the EPM9560RZ208-15 is a mature, qualified choice.
推荐
ISA/PCI Bus Address Decoding
The EPM9560RZ208-15 fits ISA and PCI bus address-decoding applications because its 560 macrocells can decode the full 32-bit address space of a PCI bus while also providing bus-master arbitration, interrupt steering, and wait-state generation in a single device. The 15 ns tPD easily meets the PCI 33 MHz clock-to-output requirements with margin to spare, while the 212 user I/Os comfortably accommodate the PCI bus signals plus several ISA or local-bus peripherals. The non-volatile configuration eliminates the boot-time delay associated with SRAM-based FPGAs — important for systems that must respond to bus arbitration within microseconds of power-up. The deterministic timing model also allows designers to compute worst-case propagation paths without iteration, accelerating board bring-up. Compared to discrete 74F138 / 74F139 decoder trees, a single MAX 9560 reduces part count, lowers propagation skew, and provides a software-configurable decode map that can be revised without PCB changes. This makes the EPM9560RZ208-15 a standard choice for industrial-PCI and CompactPCI single-board computers.
推荐
Microcontroller Peripheral Expansion
The EPM9560RZ208-15 fits microcontroller peripheral-expansion applications because it can synthesize custom peripherals — PWM generators, quadrature decoders, UARTs, and chip-select glue — that extend a host MCU's I/O count and offload timing-critical tasks. The 560 macrocells provide ample capacity for 8–10 synthesized peripherals in a single device, while the 212 user I/Os comfortably handle the multiplexed signal fan-out to sensors, actuators, and external memory. The 5V-tolerant I/Os on most MAX 9000 variants interface directly with 5V MCUs without level shifters, simplifying board design. The non-volatile EEPROM configuration means the peripheral map is available instantly on power-up — important for deterministic motor-control and safety-critical loops. Compared to discrete logic implementations, the MAX 9560 consolidates 10–20 small ICs into one, reducing PCB area by 50–70% and BOM cost. The EPM9560RZ208-15 is widely used in industrial automation, robotics, and embedded control designs where deterministic peripheral behavior is required.
推荐
ASIC Prototyping and Logic Consolidation
The EPM9560RZ208-15 fits ASIC prototyping and logic-consolidation applications because its 12,000 usable gates are sufficient to emulate a small block of a planned gate-array or structured-ASIC design, allowing firmware and system validation to proceed in parallel with ASIC fab. The deterministic timing of the FastTrack interconnect lets designers verify worst-case critical paths against ASIC timing budgets before tape-out, reducing design risk. The 212 user I/Os accommodate the wide busses typical of ASIC datapaths (32–64 bits plus control), and the 5V I/O compatibility simplifies integration with legacy test fixtures. The non-volatile configuration means prototypes can be reprogrammed and reused across multiple ASIC iterations without external PROMs. Compared to FPGA prototyping, the MAX 9560 consumes less power and is less expensive at low volumes, though it has lower density. This makes the EPM9560RZ208-15 a standard choice for prototyping glue logic and peripheral controllers ahead of ASIC migration.
推荐
Legacy Board Repair and Last-Time-Buy Stock
The EPM9560RZ208-15 fits legacy board-repair and last-time-buy stock scenarios because production systems that integrated this part in the late-1990s and 2000s often require functional-equivalent replacements during maintenance cycles. The 560 macrocells, 212 user I/Os, and 15 ns tPD match the exact specifications of the originally-installed part, ensuring that the repaired system performs identically to the original. The RQFP-208 package footprint matches existing PCB land patterns, so no board rework is required. The non-volatile EEPROM configuration ensures the repaired unit behaves identically to the original after programming. Compared to redesigning with a modern CPLD (which would require board respin, requalification, and possibly FCC/CE re-certification), sourcing the same EPM9560RZ208-15 minimizes repair cost and turnaround. This is the primary use case for this part in 2026 — supporting installed-base systems in industrial, telecom, and military/aerospace markets with long service lifetimes.
推荐
推荐产品汇总
工程参考数据： EPM9560RZ208-15 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM9560RI208-15 | EPM9560RI208-20 | EPM9560RI208-10 | EPM9560RC208-15 | EPM9480RC208-15 | EPM9400RC208-20 |
|---|---|---|---|---|---|---|---|
| Package | RQFP-208 (PowerQuad QFP) | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | QFP-208 - different outline | QFP-208 - different outline | QFP-208 - different outline |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 480 (-14%) | 400 (-29%) |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 10,000 | 8,000 |
| Pin-to-Pin Delay (tPD) | 15 ns | 15 ns (same) | 20 ns (slower) | 10 ns (faster) | 15 ns (same) | 15 ns (same) | 20 ns (slower) |
| Family | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
关键差异点
- Higher logic density in the same MAX 9000 family （对比 EPM9480RC208-15)
- PowerQuad QFP package for low-profile designs （对比 EPM9560RC208-15)
- 15 ns speed grade matches the design's synchronous clock budget （对比 EPM9560RI208-20)
设计说明
The RQFP-208 (PowerQuad QFP) package uses a 0.5 mm lead pitch with thermal pad considerations. Recommended PCB land pattern is per IPC-7351 nominal density with 0.6 mm pad width. Place a continuous ground plane on the layer immediately beneath the device to provide a low-impedance return path for the high-pin-count I/O. Decoupling: 0.1 µF ceramic capacitor within 5 mm of each VCC/GND pair, plus a single 10 µF tantalum or polymer bulk capacitor near the device. For mixed 5V/3.3V designs, isolate the MAX 9560 VCCIO bank supply from other 3.3V logic with a ferrite bead to prevent ground bounce coupling through the shared plane.
Estimated: at 33 MHz toggle frequency across 50% of 212 I/Os with 50 pF load, the dynamic power consumption is approximately P = 0.5 × C × V^2 × f × N = 0.5 × 50e-12 × 25 × 33e6 × 106 ≈ 2.2 W. Add quiescent power (~150 mA × 5V = 0.75 W typical) for a total estimated dissipation of ~3 W. The RQFP-208 has a θJA of approximately 25-30 °C/W with 1 oz copper 4-layer board and thermal vias — resulting in a junction temperature rise of ~75-90 °C above ambient at full load. For high-altitude or sealed-enclosure applications, derate toggle activity by 20% or attach a clip-on heatsink to the package top.
Do not assume the EPM9560RZ208-15 is pin-compatible with the EPM9560RC208-15 — the RZ suffix indicates a PowerQuad QFP (RQFP) package with different mechanical outline and pin numbering compared to the standard QFP-208 used by the RC suffix. Verify the original board's package marking before substituting. Also note that MAX 9000 devices require 5V VCC (not 3.3V); connecting 3.3V-only will prevent configuration and may damage the device. JTAG programming requires the four JTAG pins (TDI/TDO/TMS/TCK) to be accessible — ensure they are not assigned to user I/O functions in the Quartus pin assignment file unless pull-ups are provided externally.
合规信息
Compliance information not present in the verified web data; the EPM9560RZ208-15 is a mature Altera (Intel) part and original-era MAX 9000 devices were typically non-RoHS. Verify with the manufacturer or distributor documentation before using in RoHS-restricted designs.
