EPM9560RZ208-15 - MAX 9000 EPLD, 560 Logic Elements | Altera
MPN: EPM9560RZ208-15 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $85 | $85.00 |
| 10 | $76.5 | $765.00 |
| 100 | $68 | $6,800.00 |
| 500 | $61.2 | $30,600.00 |
| 1,000 | $55 | $55,000.00 |
Drop-in alternatives for EPM9560RZ208-15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9560RI208-15
✅ Drop-In✓ In Stock
$20.1 / Unit
View Datasheet →EPM9560RI208-20
✅ Drop-In✓ In Stock
$21.1 / Unit
View Datasheet →EPM9560RI208-10
✅ Drop-In✓ In Stock
$67.8 / Unit
View Datasheet →EPM9560RC208-15
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Contact for price
View Datasheet →EPM9480RC208-15
✅ Drop-In✓ In Stock
$24.95 / Unit
View Datasheet →EPM9400RC208-20
✅ Drop-In✓ In Stock
$60.49 / Unit
View Datasheet →EPM9560RZ208-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks (LABs) | 16 |
| User I/O Pins (max) | 212 |
| Package | RQFP-208 (PowerQuad QFP) |
| Speed Grade | -15 (15 ns pin-to-pin delay) |
| Process Technology | 0.35 µm CMOS EEPROM |
| Operating Voltage (Core) | 5.0 V |
| Programmability | In-System Programmable (ISP) via JTAG |
| Pin-to-Pin Delay (tPD) | 15 ns |
| Mounting Type | Surface Mount |
EPM9560RZ208-15 Pin Configuration
| Pin 1 | GND — Ground reference (TQFP convention - check datasheet for exact assignment) |
| Pin 2 | I/O — User I/O pin (function assigned by Quartus design) |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | I/O — User I/O pin |
| Pin 7 | I/O — User I/O pin |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | I/O — User I/O pin |
| Pin 10 | I/O — User I/O pin |
| Pin 11 | I/O — User I/O pin |
| Pin 12 | I/O — User I/O pin |
| Pin 13 | I/O — User I/O pin |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | I/O — User I/O pin |
| Pin 16 | GND — Ground reference |
| Pin 17 | I/O — User I/O pin |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | I/O — User I/O pin |
| Pin 20 | I/O — User I/O pin |
| Pin 21 | I/O — User I/O pin |
| Pin 22 | I/O — User I/O pin |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | I/O — User I/O pin |
| Pin 26 | I/O — User I/O pin |
| Pin 27 | I/O — User I/O pin |
| Pin 28 | VCC — +5V core supply |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | I/O — User I/O pin |
| Pin 31 | I/O — User I/O pin |
| Pin 32 | I/O — User I/O pin |
| Pin 33 | I/O — User I/O pin |
| Pin 34 | I/O — User I/O pin |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | I/O — User I/O pin |
| Pin 37 | I/O — User I/O pin |
| Pin 38 | I/O — User I/O pin |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | I/O — User I/O pin |
| Pin 41 | I/O — User I/O pin |
| Pin 42 | I/O — User I/O pin |
| Pin 43 | I/O — User I/O pin |
| Pin 44 | I/O — User I/O pin |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | I/O — User I/O pin |
| Pin 47 | I/O — User I/O pin |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | I/O — User I/O pin |
| Pin 51 | I/O — User I/O pin |
| Pin 52 | GND — Ground reference |
| Pin 53 | I/O — User I/O pin |
| Pin 54 | I/O — User I/O pin |
| Pin 55 | I/O — User I/O pin |
| Pin 56 | I/O — User I/O pin |
| Pin 57 | I/O — User I/O pin |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | I/O — User I/O pin |
| Pin 61 | I/O — User I/O pin |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | I/O — User I/O pin |
| Pin 64 | I/O — User I/O pin |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | I/O — User I/O pin |
| Pin 67 | I/O — User I/O pin |
| Pin 68 | I/O — User I/O pin |
| Pin 69 | I/O — User I/O pin |
| Pin 70 | I/O — User I/O pin |
| Pin 71 | I/O — User I/O pin |
| Pin 72 | I/O — User I/O pin |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | I/O — User I/O pin |
| Pin 75 | I/O — User I/O pin |
| Pin 76 | I/O — User I/O pin |
| Pin 77 | TDI — JTAG Test Data In |
| Pin 78 | TMS — JTAG Test Mode Select |
| Pin 79 | TCK — JTAG Test Clock |
| Pin 80 | TDO — JTAG Test Data Out |
| Pin 81 | I/O — User I/O pin |
| Pin 82 | I/O — User I/O pin |
| Pin 83 | I/O — User I/O pin |
| Pin 84 | I/O — User I/O pin |
| Pin 85 | I/O — User I/O pin |
| Pin 86 | I/O — User I/O pin |
| Pin 87 | I/O — User I/O pin |
| Pin 88 | GND — Ground reference |
| Pin 89 | I/O — User I/O pin |
| Pin 90 | I/O — User I/O pin |
| Pin 91 | I/O — User I/O pin |
| Pin 92 | I/O — User I/O pin |
| Pin 93 | I/O — User I/O pin |
| Pin 94 | I/O — User I/O pin |
| Pin 95 | I/O — User I/O pin |
| Pin 96 | I/O — User I/O pin |
| Pin 97 | I/O — User I/O pin |
| Pin 98 | I/O — User I/O pin |
| Pin 99 | I/O — User I/O pin |
| Pin 100 | I/O — User I/O pin |
| Pin 101 | I/O — User I/O pin |
| Pin 102 | I/O — User I/O pin |
| Pin 103 | I/O — User I/O pin |
| Pin 104 | I/O — User I/O pin |
| Pin 105 | I/O — User I/O pin |
| Pin 106 | I/O — User I/O pin |
| Pin 107 | I/O — User I/O pin |
| Pin 108 | I/O — User I/O pin |
| Pin 109 | I/O — User I/O pin |
| Pin 110 | I/O — User I/O pin |
| Pin 111 | I/O — User I/O pin |
| Pin 112 | I/O — User I/O pin |
| Pin 113 | I/O — User I/O pin |
| Pin 114 | I/O — User I/O pin |
| Pin 115 | I/O — User I/O pin |
| Pin 116 | I/O — User I/O pin |
| Pin 117 | I/O — User I/O pin |
| Pin 118 | I/O — User I/O pin |
| Pin 119 | I/O — User I/O pin |
| Pin 120 | I/O — User I/O pin |
| Pin 121 | I/O — User I/O pin |
| Pin 122 | I/O — User I/O pin |
| Pin 123 | I/O — User I/O pin |
| Pin 124 | I/O — User I/O pin |
| Pin 125 | I/O — User I/O pin |
| Pin 126 | I/O — User I/O pin |
| Pin 127 | I/O — User I/O pin |
| Pin 128 | GND — Ground reference |
| Pin 129 | I/O — User I/O pin |
| Pin 130 | I/O — User I/O pin |
| Pin 131 | I/O — User I/O pin |
| Pin 132 | I/O — User I/O pin |
| Pin 133 | I/O — User I/O pin |
| Pin 134 | I/O — User I/O pin |
| Pin 135 | I/O — User I/O pin |
| Pin 136 | I/O — User I/O pin |
| Pin 137 | I/O — User I/O pin |
| Pin 138 | I/O — User I/O pin |
| Pin 139 | I/O — User I/O pin |
| Pin 140 | I/O — User I/O pin |
| Pin 141 | I/O — User I/O pin |
| Pin 142 | I/O — User I/O pin |
| Pin 143 | I/O — User I/O pin |
| Pin 144 | I/O — User I/O pin |
| Pin 145 | I/O — User I/O pin |
| Pin 146 | I/O — User I/O pin |
| Pin 147 | I/O — User I/O pin |
| Pin 148 | I/O — User I/O pin |
| Pin 149 | I/O — User I/O pin |
| Pin 150 | I/O — User I/O pin |
| Pin 151 | I/O — User I/O pin |
| Pin 152 | I/O — User I/O pin |
| Pin 153 | I/O — User I/O pin |
| Pin 154 | VCC — +5V core supply |
| Pin 155 | I/O — User I/O pin |
| Pin 156 | I/O — User I/O pin |
| Pin 157 | I/O — User I/O pin |
| Pin 158 | I/O — User I/O pin |
| Pin 159 | I/O — User I/O pin |
| Pin 160 | I/O — User I/O pin |
| Pin 161 | I/O — User I/O pin |
| Pin 162 | I/O — User I/O pin |
| Pin 163 | I/O — User I/O pin |
| Pin 164 | I/O — User I/O pin |
| Pin 165 | I/O — User I/O pin |
| Pin 166 | I/O — User I/O pin |
| Pin 167 | I/O — User I/O pin |
| Pin 168 | I/O — User I/O pin |
| Pin 169 | I/O — User I/O pin |
| Pin 170 | I/O — User I/O pin |
| Pin 171 | I/O — User I/O pin |
| Pin 172 | I/O — User I/O pin |
| Pin 173 | I/O — User I/O pin |
| Pin 174 | I/O — User I/O pin |
| Pin 175 | I/O — User I/O pin |
| Pin 176 | I/O — User I/O pin |
| Pin 177 | I/O — User I/O pin |
| Pin 178 | I/O — User I/O pin |
| Pin 179 | I/O — User I/O pin |
| Pin 180 | I/O — User I/O pin |
| Pin 181 | I/O — User I/O pin |
| Pin 182 | GND — Ground reference |
| Pin 183 | I/O — User I/O pin |
| Pin 184 | I/O — User I/O pin |
| Pin 185 | I/O — User I/O pin |
| Pin 186 | I/O — User I/O pin |
| Pin 187 | I/O — User I/O pin |
| Pin 188 | I/O — User I/O pin |
| Pin 189 | I/O — User I/O pin |
| Pin 190 | I/O — User I/O pin |
| Pin 191 | I/O — User I/O pin |
| Pin 192 | I/O — User I/O pin |
| Pin 193 | I/O — User I/O pin |
| Pin 194 | I/O — User I/O pin |
| Pin 195 | I/O — User I/O pin |
| Pin 196 | I/O — User I/O pin |
| Pin 197 | I/O — User I/O pin |
| Pin 198 | I/O — User I/O pin |
| Pin 199 | I/O — User I/O pin |
| Pin 200 | I/O — User I/O pin |
| Pin 201 | I/O — User I/O pin |
| Pin 202 | I/O — User I/O pin |
| Pin 203 | I/O — User I/O pin |
| Pin 204 | I/O — User I/O pin |
| Pin 205 | I/O — User I/O pin |
| Pin 206 | I/O — User I/O pin |
| Pin 207 | I/O — User I/O pin |
| Pin 208 | I/O — User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RZ208-15 is suitable for 6 applications: Legacy Industrial Control Systems, Telecommunications Backplane Glue Logic, ISA/PCI Bus Address Decoding, Microcontroller Peripheral Expansion, ASIC Prototyping and Logic Consolidation, Legacy Board Repair and Last-Time-Buy Stock.
Legacy Industrial Control Systems
The EPM9560RZ208-15 fits legacy industrial control systems because its 560 macrocells and 212 user I/Os can replace dozens of discrete 74-series logic devices on a control board, dramatically reducing component count and improving reliability. The device's 15 ns tPD comfortably supports 33 MHz synchronous operation typical of PLC backplanes, motor-control interfaces, and sensor-multiplexing boards. The RQFP-208 package's surface-mount profile also suits modernized control cabinets where vibration resistance is critical. Compared to a discrete logic implementation, a single MAX 9560 reduces PCB area by 60–80% and simplifies BOM management. The device's non-volatile EEPROM configuration means no external boot PROM is required — power-on behavior is deterministic. This makes the EPM9560RZ208-15 a strong candidate for repairing or extending legacy control systems whose original CPLD has failed or whose logic must be updated to support new sensor types.
Recommended
Telecommunications Backplane Glue Logic
The EPM9560RZ208-15 fits telecommunications backplane glue-logic applications because its high I/O count (212 pins) can simultaneously address multiple bus segments, control line interfaces, and timing-synchronization signals on a backplane mid-plane. The deterministic tPD = 15 ns timing enables the device to reliably bridge 33 MHz TDM buses, E1/T1 framers, and HDLC controllers without violating setup/hold budgets. The FastTrack continuous interconnect ensures every signal path has the same delay regardless of placement — a critical property for backplane designs where signal-integrity margins are tight. Compared to FPGA alternatives, the MAX 9560's instant-on (no configuration time) and 5V-tolerant I/Os make it simpler to integrate with legacy line-interface units. The RQFP-208 package supports the high pin density required for backplane glue logic. For TDM and SDH backplanes operating at speeds up to 52 Mbps, the EPM9560RZ208-15 is a mature, qualified choice.
Recommended
ISA/PCI Bus Address Decoding
The EPM9560RZ208-15 fits ISA and PCI bus address-decoding applications because its 560 macrocells can decode the full 32-bit address space of a PCI bus while also providing bus-master arbitration, interrupt steering, and wait-state generation in a single device. The 15 ns tPD easily meets the PCI 33 MHz clock-to-output requirements with margin to spare, while the 212 user I/Os comfortably accommodate the PCI bus signals plus several ISA or local-bus peripherals. The non-volatile configuration eliminates the boot-time delay associated with SRAM-based FPGAs — important for systems that must respond to bus arbitration within microseconds of power-up. The deterministic timing model also allows designers to compute worst-case propagation paths without iteration, accelerating board bring-up. Compared to discrete 74F138 / 74F139 decoder trees, a single MAX 9560 reduces part count, lowers propagation skew, and provides a software-configurable decode map that can be revised without PCB changes. This makes the EPM9560RZ208-15 a standard choice for industrial-PCI and CompactPCI single-board computers.
Recommended
Microcontroller Peripheral Expansion
The EPM9560RZ208-15 fits microcontroller peripheral-expansion applications because it can synthesize custom peripherals — PWM generators, quadrature decoders, UARTs, and chip-select glue — that extend a host MCU's I/O count and offload timing-critical tasks. The 560 macrocells provide ample capacity for 8–10 synthesized peripherals in a single device, while the 212 user I/Os comfortably handle the multiplexed signal fan-out to sensors, actuators, and external memory. The 5V-tolerant I/Os on most MAX 9000 variants interface directly with 5V MCUs without level shifters, simplifying board design. The non-volatile EEPROM configuration means the peripheral map is available instantly on power-up — important for deterministic motor-control and safety-critical loops. Compared to discrete logic implementations, the MAX 9560 consolidates 10–20 small ICs into one, reducing PCB area by 50–70% and BOM cost. The EPM9560RZ208-15 is widely used in industrial automation, robotics, and embedded control designs where deterministic peripheral behavior is required.
Recommended
ASIC Prototyping and Logic Consolidation
The EPM9560RZ208-15 fits ASIC prototyping and logic-consolidation applications because its 12,000 usable gates are sufficient to emulate a small block of a planned gate-array or structured-ASIC design, allowing firmware and system validation to proceed in parallel with ASIC fab. The deterministic timing of the FastTrack interconnect lets designers verify worst-case critical paths against ASIC timing budgets before tape-out, reducing design risk. The 212 user I/Os accommodate the wide busses typical of ASIC datapaths (32–64 bits plus control), and the 5V I/O compatibility simplifies integration with legacy test fixtures. The non-volatile configuration means prototypes can be reprogrammed and reused across multiple ASIC iterations without external PROMs. Compared to FPGA prototyping, the MAX 9560 consumes less power and is less expensive at low volumes, though it has lower density. This makes the EPM9560RZ208-15 a standard choice for prototyping glue logic and peripheral controllers ahead of ASIC migration.
Recommended
Legacy Board Repair and Last-Time-Buy Stock
The EPM9560RZ208-15 fits legacy board-repair and last-time-buy stock scenarios because production systems that integrated this part in the late-1990s and 2000s often require functional-equivalent replacements during maintenance cycles. The 560 macrocells, 212 user I/Os, and 15 ns tPD match the exact specifications of the originally-installed part, ensuring that the repaired system performs identically to the original. The RQFP-208 package footprint matches existing PCB land patterns, so no board rework is required. The non-volatile EEPROM configuration ensures the repaired unit behaves identically to the original after programming. Compared to redesigning with a modern CPLD (which would require board respin, requalification, and possibly FCC/CE re-certification), sourcing the same EPM9560RZ208-15 minimizes repair cost and turnaround. This is the primary use case for this part in 2026 — supporting installed-base systems in industrial, telecom, and military/aerospace markets with long service lifetimes.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RZ208-15 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RI208-15 | EPM9560RI208-20 | EPM9560RI208-10 | EPM9560RC208-15 | EPM9480RC208-15 | EPM9400RC208-20 |
|---|---|---|---|---|---|---|---|
| Package | RQFP-208 (PowerQuad QFP) | RQFP-208 - same | RQFP-208 - same | RQFP-208 - same | QFP-208 - different outline | QFP-208 - different outline | QFP-208 - different outline |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 480 (-14%) | 400 (-29%) |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 10,000 | 8,000 |
| Pin-to-Pin Delay (tPD) | 15 ns | 15 ns (same) | 20 ns (slower) | 10 ns (faster) | 15 ns (same) | 15 ns (same) | 20 ns (slower) |
| Temperature Grade | [DATA_NEEDED] | Industrial (-40C to +85C) | Industrial | Industrial | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Family | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Higher logic density in the same MAX 9000 family (vs EPM9480RC208-15)
- PowerQuad QFP package for low-profile designs (vs EPM9560RC208-15)
- 15 ns speed grade matches the design's synchronous clock budget (vs EPM9560RI208-20)
Design Notes
The RQFP-208 (PowerQuad QFP) package uses a 0.5 mm lead pitch with thermal pad considerations. Recommended PCB land pattern is per IPC-7351 nominal density with 0.6 mm pad width. Place a continuous ground plane on the layer immediately beneath the device to provide a low-impedance return path for the high-pin-count I/O. Decoupling: 0.1 µF ceramic capacitor within 5 mm of each VCC/GND pair, plus a single 10 µF tantalum or polymer bulk capacitor near the device. For mixed 5V/3.3V designs, isolate the MAX 9560 VCCIO bank supply from other 3.3V logic with a ferrite bead to prevent ground bounce coupling through the shared plane.
Estimated: at 33 MHz toggle frequency across 50% of 212 I/Os with 50 pF load, the dynamic power consumption is approximately P = 0.5 × C × V^2 × f × N = 0.5 × 50e-12 × 25 × 33e6 × 106 ≈ 2.2 W. Add quiescent power (~150 mA × 5V = 0.75 W typical) for a total estimated dissipation of ~3 W. The RQFP-208 has a θJA of approximately 25-30 °C/W with 1 oz copper 4-layer board and thermal vias — resulting in a junction temperature rise of ~75-90 °C above ambient at full load. For high-altitude or sealed-enclosure applications, derate toggle activity by 20% or attach a clip-on heatsink to the package top.
Do not assume the EPM9560RZ208-15 is pin-compatible with the EPM9560RC208-15 — the RZ suffix indicates a PowerQuad QFP (RQFP) package with different mechanical outline and pin numbering compared to the standard QFP-208 used by the RC suffix. Verify the original board's package marking before substituting. Also note that MAX 9000 devices require 5V VCC (not 3.3V); connecting 3.3V-only will prevent configuration and may damage the device. JTAG programming requires the four JTAG pins (TDI/TDO/TMS/TCK) to be accessible — ensure they are not assigned to user I/O functions in the Quartus pin assignment file unless pull-ups are provided externally.
Compliance Information
Compliance information not present in the verified web data; the EPM9560RZ208-15 is a mature Altera (Intel) part and original-era MAX 9000 devices were typically non-RoHS. Verify with the manufacturer or distributor documentation before using in RoHS-restricted designs.
