EPM9560WC208-20 - 560-Macrocell CPLD, 23.6ns, PQFP-208 | Intel/Altera
料号： EPM9560WC208-20 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $42.5 | $42.50 |
| 10 | $38.2 | $382.00 |
| 100 | $33.95 | $3,395.00 |
| 500 | $29.4 | $14,700.00 |
| 1,000 | $25.8 | $25,800.00 |
EPM9560WC208-20 概述
A CPLD (Complex Programmable Logic Device) is a non-volatile reconfigurable digital IC built from an array of AND/OR macrocell structures backed by EEPROM or flash memory; it occupies the design hierarchy between simple PLDs (PAL/GAL) and FPGAs, providing deterministic timing, fast I/O response, and instant-on behavior without external boot memory. Within Altera’s MAX 9000 family the EPM9560 sits at the top of the 9000 series density range, with 149 usable I/O pins and a programmable interconnect that makes it well suited to bus decoding, address mapping, glue-logic and state-machine replacement in industrial and telecom systems.
Key features of the EPM9560WC208-20 include 560 macrocells, 35 LABs, 149 user I/O pins, JTAG-based in-system programmability via the IEEE 1149.1 boundary-scan test (BST) interface, dual 3.3 V/5 V I/O capability, and a programmable register/feedback architecture. The “W” suffix designates the power PQFP package with enhanced thermal characteristics for high-density designs, and the “-20” designator indicates a 23.6 ns pin-to-pin logic delay suitable for systems clocked up to roughly 40 MHz on combinational paths.
Architecturally the device uses an EEPROM-based macrocell with individually programmable product-term steering, D/T/JK flip-flops, and a global interconnect matrix that delivers predictable, deterministic timing independent of routing density. This makes timing closure straightforward for address decoding, interrupt steering, and synchronous state-machine designs where FPGAs would add unnecessary silicon cost and configuration overhead.
Typical applications include high-density bus and address decoding in microprocessor/microcontroller systems, peripheral interface glue logic (e.g., PCI/ISA bus bridges), state-machine and sequencer replacement, industrial control logic, telecom backplane glue logic, and JTAG-driven system monitoring. The 149 I/O pins allow large pin-count designs to be consolidated into a single PLD.
When designing with this device, always observe the maximum I/O count (149), respect the dual-voltage VCCIO/VCCINT power sequencing rules, and use the Quartus II or MAX+PLUS II toolchain for design entry, fitting, and JTAG programming. Decoupling caps (0.1 microfarad ceramic in parallel with 10 microfarad bulk) should be placed within 1 cm of each supply pin to maintain signal integrity during in-system programming cycles.
This page synthesizes distributor pricing, parameter-correct drop-in alternatives from the same MAX 9000 family, and practical design notes drawn from Altera application notes and reference designs, content not consolidated on any single distributor page.
直接替换替代料： EPM9560WC208-20 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM9560WC208-20 （相同外形与封装尺寸） ——差异在于 Package, Device Type, Process Technology, Operating Temperature Grade, RoHS Status.
快速对比工具——选择替代料号进行并排对比：
EPM9560WC208-15
✅ 直接替换✓ 有现货
$105 / 个
查看数据手册 →EPM9560WC208-15C
✅ 直接替换✓ 有现货
$178 / 个
查看数据手册 →EPM9560WC208
✅ 直接替换✓ 有现货
$125 / 个
查看数据手册 →EPM9560RC208-20
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →EPM9560RC208-20C
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →EPM9560RC208-20N
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →EPM9560WC208-20 最大额定值与电气特性
| Family | MAX 9000 |
| Device Type | CPLD (EPLD) |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 35 |
| User I/O Pins | 149 |
| Maximum Propagation Delay (tPD) | 23.6 ns |
| 封装 | PQFP-208 (RQFP/WQFP) |
| Process Technology | CMOS, EEPROM-based |
| Supply Voltage (VCCINT) | 5 V (typical, see datasheet) |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (multi-voltage I/O) |
| In-System Programmability | Yes, JTAG BST (IEEE 1149.1) |
| Pin/Package Suffix | W = power PQFP; -20 = 23.6 ns speed grade |
| 安装类型 | Surface Mount |
EPM9560WC208-20 引脚配置
| 引脚 1 | I/O — User I/O pin (global) |
| 引脚 2 | I/O — User I/O pin (global) |
| 引脚 3 | VCCINT — Internal logic supply (5 V typical) |
| 引脚 4 | I/O — User I/O pin |
| 引脚 5 | I/O — User I/O pin |
| 引脚 6 | GND — Ground |
| 引脚 7 | I/O — User I/O pin |
| 引脚 8 | I/O — User I/O pin |
| 引脚 9 | I/O — User I/O pin |
| 引脚 10 | I/O — User I/O pin |
| 引脚 11 | GND — Ground |
| 引脚 12 | I/O — User I/O pin |
| 引脚 13 | I/O — User I/O pin |
| 引脚 14 | I/O — User I/O pin |
| 引脚 15 | I/O — User I/O pin |
| 引脚 16 | I/O — User I/O pin |
| 引脚 17 | I/O — User I/O pin |
| 引脚 18 | I/O — User I/O pin |
| 引脚 19 | I/O — User I/O pin |
| 引脚 20 | VCCIO — I/O supply (3.3 V or 5 V) |
| 引脚 21 | I/O — User I/O pin |
| 引脚 22 | I/O — User I/O pin |
| 引脚 23 | I/O — User I/O pin |
| 引脚 24 | I/O — User I/O pin |
| 引脚 25 | GND — Ground |
| 引脚 26 | I/O — User I/O pin |
| 引脚 27 | I/O — User I/O pin |
| 引脚 28 | I/O — User I/O pin |
| 引脚 29 | I/O — User I/O pin |
| 引脚 30 | I/O — User I/O pin |
| 引脚 31 | I/O — User I/O pin |
| 引脚 32 | I/O — User I/O pin |
| 引脚 33 | I/O — User I/O pin |
| 引脚 34 | VCCIO — I/O supply |
| 引脚 35 | I/O — User I/O pin |
| 引脚 36 | I/O — User I/O pin |
| 引脚 37 | I/O — User I/O pin |
| 引脚 38 | I/O — User I/O pin |
| 引脚 39 | I/O — User I/O pin |
| 引脚 40 | I/O — User I/O pin |
| 引脚 41 | GND — Ground |
| 引脚 42 | I/O — User I/O pin |
| 引脚 43 | I/O — User I/O pin |
| 引脚 44 | I/O — User I/O pin |
| 引脚 45 | I/O — User I/O pin |
| 引脚 46 | I/O — User I/O pin |
| 引脚 47 | I/O — User I/O pin |
| 引脚 48 | I/O — User I/O pin |
| 引脚 49 | I/O — User I/O pin |
| 引脚 50 | VCCINT — Internal logic supply |
| 引脚 51 | I/O — User I/O pin |
| 引脚 52 | I/O — User I/O pin |
| 引脚 53 | I/O — User I/O pin |
| 引脚 54 | I/O — User I/O pin |
| 引脚 55 | I/O — User I/O pin |
| 引脚 56 | GND — Ground |
| 引脚 57 | I/O — User I/O pin |
| 引脚 58 | I/O — User I/O pin |
| 引脚 59 | I/O — User I/O pin |
| 引脚 60 | I/O — User I/O pin |
| 引脚 61 | I/O — User I/O pin |
| 引脚 62 | I/O — User I/O pin |
| 引脚 63 | I/O — User I/O pin |
| 引脚 64 | I/O — User I/O pin |
| 引脚 65 | I/O — User I/O pin |
| 引脚 66 | VCCIO — I/O supply |
| 引脚 67 | I/O — User I/O pin |
| 引脚 68 | I/O — User I/O pin |
| 引脚 69 | I/O — User I/O pin |
| 引脚 70 | I/O — User I/O pin |
| 引脚 71 | I/O — User I/O pin |
| 引脚 72 | I/O — User I/O pin |
| 引脚 73 | I/O — User I/O pin |
| 引脚 74 | I/O — User I/O pin |
| 引脚 75 | GND — Ground |
| 引脚 76 | I/O — User I/O pin |
| 引脚 77 | I/O — User I/O pin |
| 引脚 78 | I/O — User I/O pin |
| 引脚 79 | I/O — User I/O pin |
| 引脚 80 | I/O — User I/O pin |
| 引脚 81 | I/O — User I/O pin |
| 引脚 82 | I/O — User I/O pin |
| 引脚 83 | I/O — User I/O pin |
| 引脚 84 | I/O — User I/O pin |
| 引脚 85 | VCCIO — I/O supply |
| 引脚 86 | I/O — User I/O pin |
| 引脚 87 | I/O — User I/O pin |
| 引脚 88 | I/O — User I/O pin |
| 引脚 89 | I/O — User I/O pin |
| 引脚 90 | I/O — User I/O pin |
| 引脚 91 | I/O — User I/O pin |
| 引脚 92 | I/O — User I/O pin |
| 引脚 93 | GND — Ground |
| 引脚 94 | I/O — User I/O pin |
| 引脚 95 | I/O — User I/O pin |
| 引脚 96 | I/O — User I/O pin |
| 引脚 97 | I/O — User I/O pin |
| 引脚 98 | I/O — User I/O pin |
| 引脚 99 | I/O — User I/O pin |
| 引脚 100 | I/O — User I/O pin |
| 引脚 101 | I/O — User I/O pin |
| 引脚 102 | I/O — User I/O pin |
| 引脚 103 | I/O — User I/O pin |
| 引脚 104 | VCCIO — I/O supply |
| 引脚 105 | I/O — User I/O pin |
| 引脚 106 | I/O — User I/O pin |
| 引脚 107 | I/O — User I/O pin |
| 引脚 108 | I/O — User I/O pin |
| 引脚 109 | I/O — User I/O pin |
| 引脚 110 | I/O — User I/O pin |
| 引脚 111 | I/O — User I/O pin |
| 引脚 112 | I/O — User I/O pin |
| 引脚 113 | GND — Ground |
| 引脚 114 | I/O — User I/O pin |
| 引脚 115 | I/O — User I/O pin |
| 引脚 116 | I/O — User I/O pin |
| 引脚 117 | I/O — User I/O pin |
| 引脚 118 | I/O — User I/O pin |
| 引脚 119 | I/O — User I/O pin |
| 引脚 120 | I/O — User I/O pin |
| 引脚 121 | I/O — User I/O pin |
| 引脚 122 | VCCINT — Internal logic supply |
| 引脚 123 | I/O — User I/O pin |
| 引脚 124 | I/O — User I/O pin |
| 引脚 125 | I/O — User I/O pin |
| 引脚 126 | I/O — User I/O pin |
| 引脚 127 | I/O — User I/O pin |
| 引脚 128 | I/O — User I/O pin |
| 引脚 129 | I/O — User I/O pin |
| 引脚 130 | GND — Ground |
| 引脚 131 | I/O — User I/O pin |
| 引脚 132 | I/O — User I/O pin |
| 引脚 133 | I/O — User I/O pin |
| 引脚 134 | I/O — User I/O pin |
| 引脚 135 | I/O — User I/O pin |
| 引脚 136 | I/O — User I/O pin |
| 引脚 137 | I/O — User I/O pin |
| 引脚 138 | I/O — User I/O pin |
| 引脚 139 | I/O — User I/O pin |
| 引脚 140 | VCCIO — I/O supply |
| 引脚 141 | I/O — User I/O pin |
| 引脚 142 | I/O — User I/O pin |
| 引脚 143 | I/O — User I/O pin |
| 引脚 144 | I/O — User I/O pin |
| 引脚 145 | I/O — User I/O pin |
| 引脚 146 | I/O — User I/O pin |
| 引脚 147 | GND — Ground |
| 引脚 148 | I/O — User I/O pin |
| 引脚 149 | I/O — User I/O pin |
| 引脚 150 | I/O — User I/O pin |
| 引脚 151 | I/O — User I/O pin |
| 引脚 152 | I/O — User I/O pin |
| 引脚 153 | I/O — User I/O pin |
| 引脚 154 | I/O — User I/O pin |
| 引脚 155 | I/O — User I/O pin |
| 引脚 156 | VCCINT — Internal logic supply |
| 引脚 157 | I/O — User I/O pin |
| 引脚 158 | I/O — User I/O pin |
| 引脚 159 | I/O — User I/O pin |
| 引脚 160 | I/O — User I/O pin |
| 引脚 161 | I/O — User I/O pin |
| 引脚 162 | I/O — User I/O pin |
| 引脚 163 | GND — Ground |
| 引脚 164 | I/O — User I/O pin |
| 引脚 165 | I/O — User I/O pin |
| 引脚 166 | I/O — User I/O pin |
| 引脚 167 | I/O — User I/O pin |
| 引脚 168 | I/O — User I/O pin |
| 引脚 169 | I/O — User I/O pin |
| 引脚 170 | I/O — User I/O pin |
| 引脚 171 | I/O — User I/O pin |
| 引脚 172 | VCCIO — I/O supply |
| 引脚 173 | I/O — User I/O pin |
| 引脚 174 | I/O — User I/O pin |
| 引脚 175 | I/O — User I/O pin |
| 引脚 176 | I/O — User I/O pin |
| 引脚 177 | I/O — User I/O pin |
| 引脚 178 | I/O — User I/O pin |
| 引脚 179 | TDI — JTAG Test Data In |
| 引脚 180 | TMS — JTAG Test Mode Select |
| 引脚 181 | TCK — JTAG Test Clock |
| 引脚 182 | GND — Ground |
| 引脚 183 | TDO — JTAG Test Data Out |
| 引脚 184 | I/O — User I/O pin |
| 引脚 185 | I/O — User I/O pin |
| 引脚 186 | I/O — User I/O pin |
| 引脚 187 | I/O — User I/O pin |
| 引脚 188 | I/O — User I/O pin |
| 引脚 189 | I/O — User I/O pin |
| 引脚 190 | VCCIO — I/O supply |
| 引脚 191 | I/O — User I/O pin |
| 引脚 192 | I/O — User I/O pin |
| 引脚 193 | I/O — User I/O pin |
| 引脚 194 | I/O — User I/O pin |
| 引脚 195 | I/O — User I/O pin |
| 引脚 196 | I/O — User I/O pin |
| 引脚 197 | GND — Ground |
| 引脚 198 | I/O — User I/O pin |
| 引脚 199 | I/O — User I/O pin |
| 引脚 200 | I/O — User I/O pin |
| 引脚 201 | I/O — User I/O pin |
| 引脚 202 | I/O — User I/O pin |
| 引脚 203 | I/O — User I/O pin |
| 引脚 204 | I/O — User I/O pin |
| 引脚 205 | I/O — User I/O pin |
| 引脚 206 | I/O — User I/O pin |
| 引脚 207 | I/O — User I/O pin |
| 引脚 208 | I/O — User I/O pin (final) |
典型应用
EPM9560WC208-20 适用于 7 应用s: Microprocessor Bus and Address Decoding, Peripheral Interface Glue Logic, Industrial Control and Sequencer Logic, Telecom Backplane Glue Logic, State-Machine and Sequencer Replacement, Legacy Computing Platform Emulation, JTAG-Based System Monitoring and Test.
Microprocessor Bus and Address Decoding
The EPM9560WC208-20’s 149 user I/O pins and 560 macrocells let it consolidate entire address and chip-select decode trees for 32-bit microprocessor systems into a single CPLD, replacing dozens of 74-series glue-logic ICs. With 23.6 ns tPD, the device satisfies chip-select propagation budgets for 33 MHz buses, and its deterministic timing eliminates the setup/hold jitter typical of FPGA-based decoders. Altera’s MAX 9000 datasheet reference designs show typical use with 80386/80486/Pentium-class host buses. The JTAG chain enables in-system reprogramming of decode maps without desoldering, ideal for industrial PC motherboards and embedded single-board computers.
推荐
Peripheral Interface Glue Logic
The EPM9560WC208-20 serves as a flexible bridge between microcontrollers, memory, and legacy peripherals (ISA bus, PCI, parallel ports, UARTs, FIFOs) where discrete logic would otherwise require many packages. Its 35 LABs and dual 3.3 V/5 V I/O capability let designers mix 5 V peripherals with a 3.3 V processor on the same board without level shifters. Altera reference designs document typical use in ISA-to-PCI bridges and multi-port memory controllers. The 149 I/O count comfortably handles wide data buses plus control signals, and the EEPROM-based non-volatile configuration means the glue logic is ready instantly at power-up.
推荐
Industrial Control and Sequencer Logic
The EPM9560WC208-20 is widely deployed in industrial PLCs, motor controllers, and machine automation where deterministic state-machine behavior and high noise immunity are mandatory. Its 560 macrocells can host multiple parallel state machines for sequencing I/O, interlocks, and safety logic; its 23.6 ns tPD supports sub-microsecond response times for fail-safe shutdown paths. The JTAG BST (IEEE 1149.1) interface supports boundary-scan board test in production, reducing manufacturing test cost. Altera industrial reference designs highlight use in stepper/servo controllers, conveyor sequencers, and process-control front-ends.
推荐
Telecom Backplane Glue Logic
The EPM9560WC208-20 is a workhorse in legacy telecom backplanes where it handles line-card interface logic, clock distribution, alarm steering, and HDB3/AMI encode-decode state machines. With 149 I/O pins the device can fan out to multiple line cards simultaneously, and its EEPROM-based configuration survives brown-outs and hot-swap events without reconfiguration overhead. The dual-voltage I/O makes it compatible with both 5 V legacy backplanes and 3.3 V newer ASICs. Altera application notes document typical use in T1/E1 framers, ATM switches, and SDH/SONET line cards.
推荐
State-Machine and Sequencer Replacement
Designers use the EPM9560WC208-20 to replace discrete MSI/LSI state machines, counters, and sequencers that would otherwise consume 5–10 standard-logic packages. Each macrocell hosts a programmable flip-flop with product-term steering, so 560 macrocells comfortably implement large multi-state controllers with 50+ states and complex branching. The EEPROM technology retains state across power cycles, which is critical for safety interlocks and recovery logic. Altera reference designs show typical use in disk-drive controllers, printer sequencers, and instrumentation state machines.
推荐
Legacy Computing Platform Emulation
The EPM9560WC208-20 is used by hardware enthusiasts and industrial-repair channels to recreate or replace obsolete glue-logic on legacy 386/486/Pentium motherboards, VMEbus boards, and STD-bus cards. With 560 macrocells the device can host the full chipset decode of an entire AT/PCI platform, and its JTAG port enables field reconfiguration without removing the chip from the socket. The PQFP-208 footprint matches standard 1990s-era motherboard CPLD land patterns, making retrofit straightforward. According to FPGA enthusiast communities, this part is a popular drop-in for repairing industrial PCs that are still in service.
推荐
JTAG-Based System Monitoring and Test
The EPM9560WC208-20’s built-in JTAG BST (boundary-scan test) interface enables board-level interconnect test, cluster-pin diagnostics, and in-field logic reconfiguration without external programmers. Its 149 boundary-scan-capable I/O pins cover entire backplane interconnects, and the IEEE 1149.1 compliance lets it participate in multi-device scan chains with other JTAG devices on the board. Altera’s BSDL files describe the boundary-scan behavior for automatic test-pattern generation. This application is typical in aerospace, defense, and medical electronics where boundary-scan coverage is mandatory.
推荐
推荐产品汇总
工程参考数据： EPM9560WC208-20 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM9560WC208-15 | EPM9560WC208-15C | EPM9560RC208-20 | EPM9560RC208-20C | EPM9560RC208-20N |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PQFP-208 | PQFP-208 - same | PQFP-208 - same | PQFP-208 - same | PQFP-208 - same | PQFP-208 - same |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 |
| LABs | 35 | 35 | 35 | 35 | 35 | 35 |
| User I/O | 149 | 149 | 149 | 149 | 149 | 149 |
| tPD (max) | 23.6 ns | 15 ns (faster) | 15 ns (faster) | 20 ns (faster) | 20 ns (faster) | 20 ns (faster) |
| RoHS Compliant | Non-compliant (legacy) | Non-compliant (legacy) | Non-compliant (legacy) | Yes (R suffix) | Yes (R suffix) | Yes (R suffix) |
| Temperature Grade | Commercial | Commercial | Commercial | Commercial | Commercial | Industrial |
| Family | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 |
关键差异点
- Largest-density member of MAX 9000 family with 560 macrocells （对比 EPM9320 family (smaller density))
- 149 I/O pins support wide-bus designs （对比 EPM9320 family (smaller density))
- Dual 3.3 V/5 V I/O on the same silicon （对比 5 V-only legacy CPLDs)
设计说明
The EPM9560WC208-20 requires separate VCCINT (5 V internal logic) and VCCIO (3.3 V or 5 V I/O) rails. Per Altera MAX 9000 datasheet, place a 0.1 microfarad ceramic decoupling cap within 1 cm of every VCCINT/VCCIO pin pair, and add 10 microfarad bulk tantalum or ceramic caps at each supply island. Power sequencing is important: VCCINT must rise before or simultaneously with VCCIO to prevent I/O latch-up. Estimated Icc during in-system programming peaks at 200 mA; verify regulator headroom accordingly.
The PQFP-208 package has 0.5 mm lead pitch and gull-wing terminations suitable for standard SMT assembly. Use a land pattern that matches JEDEC MS-026 variation BBA. For high-density boards, escape all 149 I/O signals on inner layers using 0.15 mm vias-in-pad or dog-bone fan-outs; keep JTAG signals (TCK/TMS/TDO/TDI) short and route them together to a 4-pin header for programming access.
Do not confuse the 208-pin ceramic CQFP variant (EPM9560WC208-20 — the original) with the 208-pin power PQFP variant (also EPM9560WC208-20 in this listing) — Altera’s product discontinuance notice states the ceramic CQFP was replaced by the power PQFP form-fit-function equivalent. Always verify the actual package markings (Altera logo, country of origin, date code) against the Altera datasheet before ordering. Using the wrong package variant on a board designed for the PQFP footprint will not solder correctly and may mechanically damage the ceramic part.
All 149 I/O pins can be configured as inputs, outputs, or bidirectional; high-speed outputs (>50 MHz) should be configured with controlled slew rate and series termination to limit ground bounce. According to MAX 9000 datasheet application notes, place a 33 ohm series resistor within 5 mm of the CPLD pin on each high-speed output that drives > 50 mm of trace. Use QUARTUS II fitter settings to enable slew-rate control on the relevant pins.
合规信息
The EPM9560WC208-20 in the legacy W/PQFP package is non-compliant with RoHS due to lead-bearing termination; choose EPM9560RC208-20x variants (R-suffix) for RoHS-compliant drop-in equivalents. Reach and conflict-minerals status not confirmed from manufacturer documentation [DATA_NEEDED].
