EPM5128JI - 128-Macrocell MAX 5000 UV PLD | Intel / Altera
MPN: EPM5128JI ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $29.85 | $2,985.00 |
| 500 | $26.4 | $13,200.00 |
| 1,000 | $23.95 | $23,950.00 |
Drop-in alternatives for EPM5128JI — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM5128JC
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View Datasheet →EPM5128JC-1
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View Datasheet →EPM5128JC-2
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View Datasheet →EPM5128GM883B
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View Datasheet →EPM5128GM/883B
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View Datasheet →EPM5128GI
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View Datasheet →EPM5128JI Maximum Ratings & Electrical Characteristics
| Device Family | MAX 5000 |
| Device Type | UV-erasable programmable logic device (PLD) |
| Macrocells | 128 |
| Propagation Delay (tPD) | 55 ns (typical) |
| Maximum Internal Frequency | 40 MHz |
| Process Technology | CMOS |
| Programmable Technology | UV-erasable EPROM cell |
| Package | 68-terminal ceramic CQCC, windowed, J-leads |
| Operating Temperature Grade | Industrial ("I" suffix) |
| Programming | Altera MAX+plus II compatible programmer + UV eraser |
| RoHS Status | Non-compliant (ceramic hermetic package) |
| Lead Finish | Tin-lead (SnPb) over nickel |
| Mounting Type | Surface Mount (J-lead CQCC) |
EPM5128JI 68-terminal ceramic cqcc, windowed, j-leads Pin Configuration Guide
Complete pinout information for EPM5128JI (68-terminal ceramic cqcc, windowed, j-leads package) with [DATA_NEEDED: pin count of user I/Os] pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM5128JI.
Refer to the datasheet for full pin configuration.
Estimated pin count: [DATA_NEEDED: pin count of user I/Os] pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5128JI is suitable for 6 applications: Military and Avionics Glue Logic, Industrial Control Logic, Custom State Machines, Address Decoding and Chip-Select Generation, Legacy Bus-Interface Bridging, Test and Measurement Instrumentation.
Military and Avionics Glue Logic
The EPM5128JI's hermetic ceramic windowed CQCC package and industrial temperature grade make it ideal for military and avionics glue-logic designs that must survive 20-30 year program lifetimes. With 128 macrocells and 55 ns tPD, the device easily handles address decoding, custom state machines, and bus-interface bridging between legacy microprocessors (8086, 68000, MIL-STD-1750) and modern peripherals. Designers appreciate the UV-erasable window because it allows in-field code updates on deployed avionics LRUs without replacing the PCB. Pin-to-pin compatibility across the MAX 5000 family allows easy migration between speed grades (JI -> JC-1 -> JC-2) when timing margins need tightening.
Recommended
Industrial Control Logic
Industrial control systems often integrate the EPM5128JI as custom glue logic between microcontrollers, sensors, and actuators. The 128-macrocell capacity is well-matched to PLC-style I/O expansion, encoder decoding, and protocol adaptation tasks, while the 55 ns tPD comfortably drives control-plane signals at industrial bus speeds. The CMOS process keeps standby current low, an important factor in always-on factory controllers, and the industrial temperature grade ("I" suffix) supports -40C to +85C operation typical of factory-floor enclosures. Designers can leverage existing Altera MAX+plus II toolchains still maintained in many long-running industrial programs.
Recommended
Custom State Machines
The EPM5128JI's 128 macrocells provide ample capacity for sophisticated state machines used in protocol handling, sequencer logic, and test equipment. Each macrocell contains a flip-flop and configurable combinational logic, allowing designers to encode multi-state controllers with built-in registered outputs and asynchronous reset. The 40 MHz fMAX comfortably drives state machines clocked from common reference oscillators, and the 55 ns combinational tPD is fast enough to handle decoder logic feeding the registered outputs. The windowed ceramic package supports iterative development: state machines can be erased, refined, and reprogrammed during design bring-up.
Recommended
Address Decoding and Chip-Select Generation
The EPM5128JI is widely deployed as a multi-output address decoder in legacy computer architectures. With 128 macrocells, designers can implement wide-input AND/OR decoder trees that generate 16 to 32 chip-select outputs from a 24- or 32-bit address bus, including partial-decoding and qualifier logic. The CMOS low-power design makes it well-suited to always-powered decoding, and the 55 ns tPD fits comfortably within the access-time budgets of most SRAM, ROM, and peripheral devices from the 1980s-1990s design era. Drop-in compatibility across the MAX 5000 family allows easy speed-grade migration if memory timing tightens.
Recommended
Legacy Bus-Interface Bridging
Legacy bus systems (ISA, VME, STD, Multibus) often need custom glue logic to bridge between different bus widths, signaling standards, or timing domains. The EPM5128JI's 128 macrocells handle 8-to-32 bit data steering, parity generation, and wait-state insertion logic, while its 40 MHz fMAX comfortably drives Multibus and VME architectures. The CMOS low standby current and industrial temperature grade fit industrial and military bus-interface cards, and the ceramic windowed carrier supports field updates when protocol revisions are required. Pin-to-pin compatibility across MAX 5000 speed grades allows timing-margin optimization without PCB redesign.
Recommended
Test and Measurement Instrumentation
Test and measurement instruments benefit from the EPM5128JI's combination of UV-erasable programmability, 128 macrocells of logic, and industrial temperature grade. The device is well-suited to custom timing generators, pulse-width modulators, and digital-pattern generators used in lab instrumentation, with the 55 ns tPD providing fine timing resolution. The windowed ceramic carrier allows iterative calibration logic updates as measurement algorithms evolve, and the 68-pin CQCC package supports the high-pin-count I/O required to drive parallel DACs, ADCs, and display interfaces. Long-term availability through industrial distribution channels supports 10-15 year instrument programs.
Recommended
Recommended Products Summary
Engineering reference data for EPM5128JI — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5128JC | EPM5128JC-1 | EPM5128JC-2 | EPM5128GM883B |
|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Package | 68-terminal ceramic CQCC (windowed, J-lead) | PLCC-68 (plastic) | PLCC-68 (plastic) | PLCC-68 (plastic) | Ceramic PGA-68 |
| Macrocells | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 55 ns | 55 ns | 35 ns (-1 grade) | 30 ns (-2 grade) | 55 ns |
| Maximum Frequency | 40 MHz | 40 MHz | 60 MHz | 70 MHz | 40 MHz |
| Programming Method | UV-erasable (windowed ceramic) | OTP (one-time-programmable) | OTP | OTP | UV-erasable |
| Military Screening | Industrial (no MIL-STD-883) | No | No | No | Yes (MIL-STD-883B) |
| RoHS Compliance | Non-compliant (SnPb) | Non-compliant | Non-compliant | Non-compliant | Non-compliant |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- UV-erasable ceramic windowed package (vs EPM5128JC)
- Hermetic ceramic CQCC package (vs EPM5128JC (plastic PLCC-68))
- Industrial temperature grade support (vs EPM5128GM883B (military 883B))
Design Notes
Estimated: The ceramic CQCC package of the EPM5128JI provides excellent thermal conduction through the hermetic body to the PCB. At a typical CMOS standby current of a few mA and dynamic current dominated by I/O switching, self-heating is minimal (junction temperature rise well under 5C in most designs). Designers should still provide a ground-plane thermal bond directly under the ceramic body for maximum heat spreading in sealed aerospace enclosures where ambient temperatures can reach +85C.
Place the EPM5128JI on a continuous ground plane and route all VCC and GND pins directly to the plane with short, wide traces. Maintain at least 0.1uF decoupling capacitors within 5 mm of each VCC pin pair, with a bulk 10-33uF tantalum or ceramic capacitor on the board supply rail. Because the 68-pin CQCC has fine-pitch J-leads, follow IPC-7351 CQCC land-pattern recommendations and use NSMD pads with via-in-pad or micro-via fan-out to ensure reliable solder joint formation during rework.
Do not assume the EPM5128JI is RoHS compliant - the ceramic package uses tin-lead (SnPb) finish. Do not program the device without verifying the JEDEC file matches the silicon revision, and do not skip the post-programming UV erasure window - attempting to erase through the opaque plastic cap of the JI variant will damage the device. Always design with the 55 ns tPD as the slowest timing path, and verify fMAX against MAX+plus II timing reports for any design exceeding 30 MHz internal clocks.
Route the global clock and high-speed output nets first, then the I/O banks, with 50 ohm controlled impedance if the bus exceeds 25 MHz. Keep the JTAG/programming pins (or Altera proprietary programming interface for legacy MAX 5000) accessible at the board edge for in-system programming and verification. The 68-pin CQCC is pin-compatible with PLCC-68 sockets only when an adapter is used - never assume direct PCB land-pattern compatibility between CQCC and PLCC footprints.
Compliance Information
Ceramic hermetic package uses SnPb lead finish over nickel plating; not RoHS compliant. REACH compliant per Intel/Altera legacy documentation. Not AEC-Q100 qualified (industrial temperature only). Halogen-free per package materials disclosure. Conflict-mineral reporting per Intel corporate policy.
