Intel

EPF6024ATC144-1 - 24K Gates FLEX 6000 FPGA, 144-TQFP | Intel

Référence : EPF6024ATC144-1 ✗ Fin de vie

En stock Expédié sous 1 à 3 jours ouvrés

3.3 V Vdss 144-pin TQFP Package 200 MHz Speed

À partir de $8.2 USD / unité

MOQ : 1 |

Prix mis à jour : 2026-09-11

Tarifs dégressifs

Qté	Prix unitaire	Total
1	$18.5	$18,50
10	$15.95	$159,50
100	$12.4	$1 240,00
500	$9.85	$4 925,00
1 000	$8.2	$8 200,00

ℹ️ Tous les prix sont en USD

Voir la fiche technique (PDF) Voir les alternatives

Quantité

EPF6024ATC144-1 Présentation

The Intel (formerly Altera) EPF6024ATC144-1 is a member of the FLEX 6000 family of CMOS SRAM-based programmable logic devices, providing 24,000 usable gates, 1,960 logic elements, and 117 user I/Os in a 144-pin TQFP package. Built on a 0.42 um CMOS process and operating from a 3.3 V supply, the device integrates 196 LABs (Logic Array Blocks) for high-density combinational and sequential logic implementation. The '-1' speed grade places it in the standard performance tier of the family, suitable for general-purpose glue logic, bus interfacing, and state-machine control.

What is a FLEX 6000 FPGA? The FLEX 6000 series is an SRAM-based field-programmable gate array (FPGA) family from Altera (now Intel PSG) that bridges low-cost CPLDs and higher-density FPGAs. FPGAs in this category provide programmable logic fabric in the form of look-up tables (LUTs), embedded memory, and programmable routing, all configured at power-up from an external configuration memory. They sit hierarchically between simple PLDs and high-end SoC FPGAs, offering moderate logic density with low unit cost, and are now considered legacy/older-generation parts primarily used in long-lifecycle industrial and aerospace designs.

Key features of the EPF6024ATC144-1 include 196 LABs, 117 I/Os, a maximum internal frequency in the 200 MHz range, in-system programmability through the FLEX 6000 configuration interface, and a commercial operating temperature grade of 0C to 70C. The device supports 3.3 V LVTTL/LVCMOS I/O standards and exposes JTAG (IEEE 1149.1) boundary-scan pins for board test access.

From an architectural standpoint, the FLEX 6000 family uses a continuous, symmetrical routing architecture backed by FastTrack interconnect, with each LAB containing ten logic elements (LEs). Configuration data is loaded serially or via the dedicated configuration port, and the design flow uses the legacy MAX+PLUS II or Quartus (legacy device support) toolchain.

Typical applications for the EPF6024ATC144-1 include industrial control glue logic, parallel-to-serial bus bridges, legacy peripheral emulation, ASIC prototyping in cost-sensitive systems, and avionics upgrades where a pin-compatible 3.3 V FPGA is required. Today the part is generally sourced from the secondary/aftermarket channel and used to sustain long-life equipment.

Designers should note that FLEX 6000 devices require an external configuration EPROM (such as the EPC2 or EPC8) or a microcontroller-driven configuration scheme; the FPGA itself does not retain configuration through power cycles. Verify timing closure using the MAX+PLUS II timing analyzer or Quartus legacy support tools, and ensure the JTAG chain is properly terminated for board-level testability.

This page consolidates distributor stock, pricing, drop-in alternative MPNs, and engineering design notes - information not aggregated on the manufacturer's legacy datasheet alone.

Alternatives de remplacement direct pour EPF6024ATC144-1 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.

Variantes de cette série

Modèles de la même série directement compatibles avec EPF6024ATC144-1 (même facteur de forme et même empreinte) — différant par Package, Speed Grade, Operating Temperature, Process Technology, Configuration Method.

EPF6010ATC144-1

Intel

Package: 144-LQFP / TQFP-144 (20x20 mm)

Operating Temperature: 0 °C to +85 °C (commercial)

Process Technology: 0.42 µm CMOS