Altera

EPM570ZM100I8N - 440-Macrocell MAX II CPLD, 100-BGA | Intel / Altera

Référence : EPM570ZM100I8N ✓ Actif

En stock Expédié sous 1 à 3 jours ouvrés

1.8 V Vdss 100-ball FineLine BGA (MBGA, 0.8 mm pitch) Package 152 MHz Speed

À partir de $16.5 USD / unité

MOQ : 1 |

Prix mis à jour : 2026-09-12

Tarifs dégressifs

Qté	Prix unitaire	Total
1	$26.42	$26,42
10	$23.78	$237,80
100	$21.13	$2 113,00
500	$18.49	$9 245,00
1 000	$16.5	$16 500,00

ℹ️ Tous les prix sont en USD

Voir la fiche technique (PDF) Voir les alternatives

Quantité

EPM570ZM100I8N Présentation

The Intel / Altera EPM570ZM100I8N is a 440-macrocell MAX II zero-power CPLD delivering up to 152 MHz internal operation and 76 user I/O, packaged in a 100-ball FineLine BGA (MBGA). Part of the MAX II device family, the EPM570Z variant features a 1.8 V core supply and non-volatile flash configuration memory that eliminates the external configuration PROM normally required by SRAM-based CPLDs.

What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile, low-density programmable logic device that sits architecturally between discrete logic gates (74HC, 74LV) and FPGAs. CPLDs typically contain a few hundred to a few thousand macrocells organized into Logic Array Blocks (LABs) with a deterministic, non-volatile interconnect fabric. Compared to FPGAs, CPLDs have lower logic density, lower power consumption, instant-on configuration (< 1 ms), and a more predictable timing model that simplifies timing closure for glue-logic and bus-interface designs.

Key features of the EPM570ZM100I8N include 570 Logic Elements, 57 LABs, 440 macrocells, 76 user I/Os, JTAG-compliant IEEE 1149.1 boundary-scan support, in-system programmability (ISP) via JTAG, a chip-wide DEV_OE output-enable pin, and on-chip flash user flash memory for user data storage. The MAX II family is built on a 0.18 μm flash process and is specified for the industrial -40 °C to +85 °C temperature range.

Typical applications include bus-interface bridging (for example, address-latch or chip-select decoding in legacy microprocessor systems), power-sequencer logic, I/O expansion for microcontrollers, LED-display drivers, and configurable glue logic in industrial-control boards where the non-volatile, instant-on behavior of a CPLD is more attractive than an FPGA's configuration delay.

When designing with this device, ensure PCB layout accommodates the 0.8 mm pitch FineLine BGA and that JTAG pins (TCK, TMS, TDI, TDO) are brought out to a test header. The EPM570Z's 1.8 V core must be supplied independently from the 3.3 V or 2.5 V I/O bank supply used by surrounding logic. Always reference the Altera MAX II Device Handbook for timing-model parameters.

Alternatives de remplacement direct pour EPM570ZM100I8N — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.

Variantes de cette série

Modèles de la même série directement compatibles avec EPM570ZM100I8N (même facteur de forme et même empreinte) — différant par Series, Operating Temperature, Package, Process Technology, Logic Elements.

5M240ZM68I5N

Intel

Series: MAX V

Logic Elements: 240