Intel

EPM7128SQC160-15N - 128-Macro 15ns CPLD MAX 7000 | Intel / Altera

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5 V Vdss 160-pin PQFP / BQFP (Plastic Quad Flat Pack) Package 76.9 MHz Speed

À partir de $23 USD / unité

MOQ : 1 |

Prix mis à jour : 2026-09-12

Tarifs dégressifs

Qté	Prix unitaire	Total
1	$44.11	$44,11
10	$39.7	$397,00
100	$33.1	$3 310,00
500	$27.6	$13 800,00
1 000	$23	$23 000,00

ℹ️ Tous les prix sont en USD

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EPM7128SQC160-15N Présentation

The Intel / Altera (formerly Altera) EPM7128SQC160-15N is a 128-macrocell, 100-IO Complex Programmable Logic Device (CPLD) from the second-generation MAX 7000 family, housed in a 160-pin Plastic Quad Flat Pack (PQFP-160 / BQFP-160) package. Built on a 5V-tolerant CMOS EEPROM process, it provides 15ns pin-to-pin logic delay, a 76.9 MHz internal counter frequency, and 2.5K usable gates, making it suitable for medium-density glue-logic and bus-interface applications.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the instant-on characteristics of PAL/GAL architecture with the density of a small FPGA. Within the broader programmable-logic taxonomy, CPLDs sit between discrete PALs (small, simple, fast) and FPGAs (large, register-rich, SRAM-based). The MAX 7000 family was Altera's second-generation CPLD architecture (succeeding the classic MAX 5000/9000) and introduced the multi-matrix interconnect plus ISP (in-system programmability) via JTAG, features that made it the de-facto industry standard for glue logic from the mid-1990s onward.

Key features of the EPM7128SQC160-15N include 128 macrocells arranged in 8 logic array blocks (LABs), 100 user I/O pins, 15ns combinatorial propagation delay, a maximum internal counter frequency of 76.9 MHz, and 5V-tolerant I/O supporting both 3.3V and 5V mixed-voltage systems. The device is non-volatile (EEPROM-based) so the configuration is retained without an external boot PROM, and it supports in-system programming via the JTAG-compatible 4-pin interface. Programmable interconnect allows wide AND-OR logic functions across LABs with predictable timing.

The architecture uses Altera's classic MAX (Multiple Array matriX) routing structure: each LAB contains 16 macrocells that share a programmable interconnect array, and LABs communicate through the PIA (Programmable Interconnect Array). This gives the EPM7128SQC160-15N deterministic, pin-locked timing that does not change with routing density - a property that distinguishes CPLDs from SRAM-based FPGAs where delay varies with placement.

Typical applications include bus-interface bridging (PCI/ISA glue logic), address decoding and chip-select generation, power-up sequencing and reset distribution, motor control peripheral logic, industrial PLC I/O expansion, and replacement of multiple discrete TTL/CMOS logic packages. The wide 5V I/O tolerance is especially valued when interfacing legacy microcontrollers or bus transceivers to modern 3.3V ASICs.

When designing with this device, note that the PQFP-160 footprint has longer lead lengths than modern BGA/QFN packages, which limits high-speed signal edge rates above ~50 MHz. For new designs above 100 MHz I/O, consider migrating to a MAX V, MAX 10, or MAX II CPLD in a smaller QFN package while preserving the MAX 7000 logic architecture.

This page synthesizes distributor pricing, SameFrame-pinout drop-in alternatives, and practical glue-logic design notes not found in the original 1998-vintage datasheet.

Alternatives de remplacement direct pour EPM7128SQC160-15N — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.

Variantes de cette série

Modèles de la même série directement compatibles avec EPM7128SQC160-15N (même facteur de forme et même empreinte) — différant par Package, Operating Temperature, Supply Voltage (VCCINT), Logic Array Blocks (LABs), Usable Gates.

EPM7128SQC100-15

Altera

Package: 100-pin PQFP (Plastic Quad Flat Pack)

Operating Temperature: 0C to +70C (Commercial)

Supply Voltage (VCCINT): 5 V (5% tolerance)