EPM7128SQC160-15N - 128-Macro 15ns CPLD MAX 7000 | Intel / Altera
MPN: EPM7128SQC160-15N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $44.11 | $44.11 |
| 10 | $39.7 | $397.00 |
| 100 | $33.1 | $3,310.00 |
| 500 | $27.6 | $13,800.00 |
| 1,000 | $23 | $23,000.00 |
Drop-in alternatives for EPM7128SQC160-15N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128SQC160-15
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEPM7128SQC160-10
β Drop-Inβ In Stock
$14.2 / Unit
View Datasheet βEPM7128SQC160-10N
β Drop-Inβ In Stock
$9.2 / Unit
View Datasheet βEPM7128SQC100-15
β Drop-Inβ In Stock
$8.2 / Unit
View Datasheet βEPM7128SQC160-15N Maximum Ratings & Electrical Characteristics
| Product Type | CPLD (Complex Programmable Logic Device) |
| Family | MAX 7000 |
| Macro Cells | 128 |
| Logic Array Blocks (LABs) | 8 |
| User I/O Count | 100 |
| Usable Gates | 2.5K |
| Propagation Delay (tPD) | 15 ns |
| Maximum Internal Frequency | 76.9 MHz |
| Supply Voltage (VCCINT) | 5 V |
| I/O Voltage Tolerance | 3.3 V / 5 V mixed |
| Programming Technology | EEPROM (non-volatile) |
| In-System Programmability | Yes (JTAG-compatible) |
| Package | 160-pin PQFP / BQFP (Plastic Quad Flat Pack) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0Β°C to +70Β°C (commercial) |
EPM7128SQC160-15N Pin Configuration
| Pin 1 | I/O β User I/O pin (function per design) |
| Pin 2 | I/O β User I/O pin (function per design) |
| Pin 3 | I/O β User I/O pin (function per design) |
| Pin 4 | I/O β User I/O pin (function per design) |
| Pin 5 | I/O β User I/O pin (function per design) |
| Pin 6 | I/O β User I/O pin (function per design) |
| Pin 7 | I/O β User I/O pin (function per design) |
| Pin 8 | I/O β User I/O pin (function per design) |
| Pin 9 | I/O β User I/O pin (function per design) |
| Pin 10 | I/O β User I/O pin (function per design) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin (function per design) |
| Pin 13 | I/O β User I/O pin (function per design) |
| Pin 14 | I/O β User I/O pin (function per design) |
| Pin 15 | I/O β User I/O pin (function per design) |
| Pin 16 | I/O β User I/O pin (function per design) |
| Pin 17 | I/O β User I/O pin (function per design) |
| Pin 18 | I/O β User I/O pin (function per design) |
| Pin 19 | I/O β User I/O pin (function per design) |
| Pin 20 | I/O β User I/O pin (function per design) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O pin (function per design) |
| Pin 23 | I/O β User I/O pin (function per design) |
| Pin 24 | I/O β User I/O pin (function per design) |
| Pin 25 | I/O β User I/O pin (function per design) |
| Pin 26 | I/O β User I/O pin (function per design) |
| Pin 27 | I/O β User I/O pin (function per design) |
| Pin 28 | I/O β User I/O pin (function per design) |
| Pin 29 | I/O β User I/O pin (function per design) |
| Pin 30 | I/O β User I/O pin (function per design) |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin (function per design) |
| Pin 33 | I/O β User I/O pin (function per design) |
| Pin 34 | I/O β User I/O pin (function per design) |
| Pin 35 | I/O β User I/O pin (function per design) |
| Pin 36 | I/O β User I/O pin (function per design) |
| Pin 37 | I/O β User I/O pin (function per design) |
| Pin 38 | I/O β User I/O pin (function per design) |
| Pin 39 | I/O β User I/O pin (function per design) |
| Pin 40 | I/O β User I/O pin (function per design) |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O pin (function per design) |
| Pin 43 | I/O β User I/O pin (function per design) |
| Pin 44 | I/O β User I/O pin (function per design) |
| Pin 45 | I/O β User I/O pin (function per design) |
| Pin 46 | I/O β User I/O pin (function per design) |
| Pin 47 | I/O β User I/O pin (function per design) |
| Pin 48 | I/O β User I/O pin (function per design) |
| Pin 49 | I/O β User I/O pin (function per design) |
| Pin 50 | I/O β User I/O pin (function per design) |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O pin (function per design) |
| Pin 53 | I/O β User I/O pin (function per design) |
| Pin 54 | I/O β User I/O pin (function per design) |
| Pin 55 | I/O β User I/O pin (function per design) |
| Pin 56 | I/O β User I/O pin (function per design) |
| Pin 57 | I/O β User I/O pin (function per design) |
| Pin 58 | I/O β User I/O pin (function per design) |
| Pin 59 | I/O β User I/O pin (function per design) |
| Pin 60 | I/O β User I/O pin (function per design) |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O pin (function per design) |
| Pin 63 | I/O β User I/O pin (function per design) |
| Pin 64 | I/O β User I/O pin (function per design) |
| Pin 65 | I/O β User I/O pin (function per design) |
| Pin 66 | I/O β User I/O pin (function per design) |
| Pin 67 | I/O β User I/O pin (function per design) |
| Pin 68 | I/O β User I/O pin (function per design) |
| Pin 69 | I/O β User I/O pin (function per design) |
| Pin 70 | I/O β User I/O pin (function per design) |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β User I/O pin (function per design) |
| Pin 73 | I/O β User I/O pin (function per design) |
| Pin 74 | I/O β User I/O pin (function per design) |
| Pin 75 | I/O β User I/O pin (function per design) |
| Pin 76 | I/O β User I/O pin (function per design) |
| Pin 77 | I/O β User I/O pin (function per design) |
| Pin 78 | I/O β User I/O pin (function per design) |
| Pin 79 | I/O β User I/O pin (function per design) |
| Pin 80 | I/O β User I/O pin (function per design) |
| Pin 81 | GND β Ground |
| Pin 82 | I/O β User I/O pin (function per design) |
| Pin 83 | I/O β User I/O pin (function per design) |
| Pin 84 | I/O β User I/O pin (function per design) |
| Pin 85 | I/O β User I/O pin (function per design) |
| Pin 86 | I/O β User I/O pin (function per design) |
| Pin 87 | I/O β User I/O pin (function per design) |
| Pin 88 | I/O β User I/O pin (function per design) |
| Pin 89 | I/O β User I/O pin (function per design) |
| Pin 90 | I/O β User I/O pin (function per design) |
| Pin 91 | GND β Ground |
| Pin 92 | I/O β User I/O pin (function per design) |
| Pin 93 | I/O β User I/O pin (function per design) |
| Pin 94 | I/O β User I/O pin (function per design) |
| Pin 95 | I/O β User I/O pin (function per design) |
| Pin 96 | I/O β User I/O pin (function per design) |
| Pin 97 | I/O β User I/O pin (function per design) |
| Pin 98 | I/O β User I/O pin (function per design) |
| Pin 99 | I/O β User I/O pin (function per design) |
| Pin 100 | I/O β User I/O pin (function per design) |
| Pin 101 | GND β Ground |
| Pin 102 | I/O β User I/O pin (function per design) |
| Pin 103 | I/O β User I/O pin (function per design) |
| Pin 104 | I/O β User I/O pin (function per design) |
| Pin 105 | I/O β User I/O pin (function per design) |
| Pin 106 | I/O β User I/O pin (function per design) |
| Pin 107 | I/O β User I/O pin (function per design) |
| Pin 108 | I/O β User I/O pin (function per design) |
| Pin 109 | I/O β User I/O pin (function per design) |
| Pin 110 | I/O β User I/O pin (function per design) |
| Pin 111 | GND β Ground |
| Pin 112 | I/O β User I/O pin (function per design) |
| Pin 113 | I/O β User I/O pin (function per design) |
| Pin 114 | I/O β User I/O pin (function per design) |
| Pin 115 | I/O β User I/O pin (function per design) |
| Pin 116 | I/O β User I/O pin (function per design) |
| Pin 117 | I/O β User I/O pin (function per design) |
| Pin 118 | I/O β User I/O pin (function per design) |
| Pin 119 | I/O β User I/O pin (function per design) |
| Pin 120 | I/O β User I/O pin (function per design) |
| Pin 121 | GND β Ground |
| Pin 122 | I/O β User I/O pin (function per design) |
| Pin 123 | I/O β User I/O pin (function per design) |
| Pin 124 | I/O β User I/O pin (function per design) |
| Pin 125 | I/O β User I/O pin (function per design) |
| Pin 126 | I/O β User I/O pin (function per design) |
| Pin 127 | I/O β User I/O pin (function per design) |
| Pin 128 | I/O β User I/O pin (function per design) |
| Pin 129 | I/O β User I/O pin (function per design) |
| Pin 130 | I/O β User I/O pin (function per design) |
| Pin 131 | GND β Ground |
| Pin 132 | I/O β User I/O pin (function per design) |
| Pin 133 | I/O β User I/O pin (function per design) |
| Pin 134 | I/O β User I/O pin (function per design) |
| Pin 135 | I/O β User I/O pin (function per design) |
| Pin 136 | I/O β User I/O pin (function per design) |
| Pin 137 | I/O β User I/O pin (function per design) |
| Pin 138 | I/O β User I/O pin (function per design) |
| Pin 139 | I/O β User I/O pin (function per design) |
| Pin 140 | I/O β User I/O pin (function per design) |
| Pin 141 | GND β Ground |
| Pin 142 | I/O β User I/O pin (function per design) |
| Pin 143 | I/O β User I/O pin (function per design) |
| Pin 144 | I/O β User I/O pin (function per design) |
| Pin 145 | I/O β User I/O pin (function per design) |
| Pin 146 | I/O β User I/O pin (function per design) |
| Pin 147 | I/O β User I/O pin (function per design) |
| Pin 148 | I/O β User I/O pin (function per design) |
| Pin 149 | I/O β User I/O pin (function per design) |
| Pin 150 | I/O β User I/O pin (function per design) |
| Pin 151 | TDI β JTAG Test Data In (dedicated) |
| Pin 152 | TMS β JTAG Test Mode Select (dedicated) |
| Pin 153 | TCK β JTAG Test Clock (dedicated) |
| Pin 154 | I/O β User I/O pin (function per design) |
| Pin 155 | I/O β User I/O pin (function per design) |
| Pin 156 | I/O β User I/O pin (function per design) |
| Pin 157 | I/O β User I/O pin (function per design) |
| Pin 158 | I/O β User I/O pin (function per design) |
| Pin 159 | TDO β JTAG Test Data Out (dedicated) |
| Pin 160 | VCC β Core + I/O supply (5 V) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128SQC160-15N is suitable for 7 applications: PCI / ISA Bus Glue Logic, Address Decoding & Chip-Select Generation, Power-Up Sequencing & Reset Distribution, Motor Control Peripheral Logic, Industrial PLC I/O Expansion, Legacy TTL / CMOS Logic Replacement, Embedded System Peripheral Bridging.
PCI / ISA Bus Glue Logic
The EPM7128SQC160-15N fits PCI/ISA bus glue-logic roles because its 128 macrocells provide ample AND-OR decoding capacity for chip-select generation, address decoding, and bus-cycle control. Its 15 ns tPD comfortably meets the 33 MHz PCI clock-to-output timing (minimum 30 ns cycle budget allows ~15 ns combinational delay), and the 100 user I/Os support the wide bus and interrupt/grant signals of legacy PC architectures. The non-volatile EEPROM configuration eliminates boot-PROM overhead - critical for instant-on BIOS extension ROMs and adapter cards. Compared to discrete 74LS/74FTTL gates, a single EPM7128SQC160-15N replaces dozens of packages, reducing PCB area and BOM cost while preserving deterministic, pin-locked timing.
Recommended
Address Decoding & Chip-Select Generation
The EPM7128SQC160-15N is widely deployed as an address decoder in microcontroller and embedded systems. Its wide AND-OR product-term architecture can decode large address ranges - up to the full 24- or 32-bit address space - in a single device, producing chip-select strobes for memory banks, peripherals, and I/O expanders. The 15 ns propagation delay ensures chip-selects are valid before the CPU's first memory-access cycle, eliminating wait-state insertion. Non-volatile EEPROM programming means the decoding map is fixed at power-up with no bootloader overhead. Compared to discrete 74HC138/139 decoders, the CPLD approach supports custom, non-power-of-two decode regions and reduces part count.
Recommended
Power-Up Sequencing & Reset Distribution
Power-up sequencing in multi-rail systems benefits from the EPM7128SQC160-15N's deterministic timing and instant-on behavior. The MAX 7000S EEPROM configuration is valid within microseconds of VCC ramp, allowing the CPLD to drive early-stage enables such as the core voltage regulator's PG (Power Good) handshakes before the main CPU resets. With 100 I/Os, it can fan out independent reset and enable signals to multiple ASICs, FPGAs, and analog rails, each gated by its own programmable time delay built from internal macrocell counters. The 5V-tolerant I/O and 3.3V/5V mixed-voltage support make it ideal for sequencing mixed-voltage boards. This usage remains common in industrial PLC backplanes and telecom line cards.
Recommended
Motor Control Peripheral Logic
Industrial motor drives use the EPM7128SQC160-15N as peripheral glue between a microcontroller/DSP and the power stage. Typical functions include PWM dead-time insertion, fault-input synchronization, encoder quadrature decoding, and gate-driver enable logic - all of which require deterministic, sub-microsecond timing that the 15 ns tPD comfortably provides. The 100 user I/Os interface to multiple Hall-effect sensors, encoder channels, and isolated gate drivers, while the 5V-tolerant I/O directly accepts 5V Hall/encoder signals without level shifters. The non-volatile EEPROM configuration survives factory-programmed motor profiles that must persist across power cycles. The MAX 7000S SameFrame footprint lets designers migrate to higher-density 256-macrocell MAX 7000S parts as control complexity grows.
Recommended
Industrial PLC I/O Expansion
PLC backplanes use the EPM7128SQC160-15N as a flexible I/O expansion and isolation interface between the central processor and field-side drivers. Its 100 user I/Os can scan a multi-module backplane, debounce mechanical contacts in hardware (via macrocell flip-flops), and present a clean register-mapped interface to the CPU. The EEPROM-based configuration lets OEMs re-flash I/O maps via JTAG without changing firmware, accelerating line-rebuild. The 5V-tolerant I/O tolerates noisy 24V field-side signals after simple resistive dividers. Industrial customers value the part's long lifecycle, wide operating range, and SameFrame migration path, even though the silicon is NRD.
Recommended
Legacy TTL / CMOS Logic Replacement
A classic use of the EPM7128SQC160-15N is consolidating dozens of discrete 74LS/74HC/74FTTL packages into a single programmable device, simplifying PCB layout and BOM. Its 128 macrocells typically replace 20-40 SSI/MSI packages while preserving exact logic function and timing. This reduces PCB layer count, assembly cost, and test time. The 5V I/O is directly compatible with legacy TTL thresholds, eliminating level translation. This use case is especially valuable in aerospace, defense, and industrial OEMs maintaining production of legacy systems where re-spinning a board for a different CPLD family would require re-certification. The EEPROM configuration is also more reliable than soldered-in discrete logic.
Recommended
Embedded System Peripheral Bridging
Bridging mismatched peripherals - for example, an 8-bit microcontroller to a 16-bit LCD bus, or a SPI master to a parallel ADC - is a natural fit for the EPM7128SQC160-15N. With 128 macrocells, the CPLD can implement protocol converters, bus-width adapters, and FIFO-like flow-control logic with deterministic timing. The 15 ns tPD easily keeps up with typical 8- and 16-bit microcontroller peripheral speeds (tens of MHz), and the 100 I/Os provide ample headroom for parallel buses. The non-volatile configuration means the bridge starts working at first power-up, even before the main CPU boots. This pattern is common in custom instrumentation and medical-device embedded boards.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128SQC160-15N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128SQC160-15 | EPM7128SQC160-10 | EPM7128SQC160-10N | EPM7128SQC100-15 |
|---|---|---|---|---|---|
| Package | PQFP-160 | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same |
| Brand | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera |
| Family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S |
| Macro Cells | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 15 ns | 15 ns | 10 ns | 10 ns | 15 ns |
| Max Internal Frequency | 76.9 MHz | 76.9 MHz | [DATA_NEEDED] | [DATA_NEEDED] | 76.9 MHz |
| User I/O | 100 | 100 | 100 | 100 | [DATA_NEEDED] |
| Lead-Free (N suffix) | Yes (N-suffix) | No (legacy leaded) | No (legacy leaded) | Yes (N-suffix) | No (legacy leaded) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Wide 5V-tolerant I/O with 3.3V/5V mixed-voltage support (vs MAX V CPLDs (e.g., 5M160ZE64))
- Non-volatile EEPROM configuration - instant-on at power-up (vs SRAM-based FPGAs (e.g., Cyclone))
- SameFrame pinout across density and package options (vs Discrete 74LS/74F TTL logic)
- Deterministic, pin-locked timing independent of routing density (vs ispMACH 4000 (Lattice))
Design Notes
PQFP-160 packages have long lead lengths (~3 mm) and significant lead inductance. Place at least one 0.1 Β΅F decoupling capacitor per VCC pin, within 5 mm of the package body. Use a continuous ground plane on the layer directly beneath the CPLD to control return-current paths and EMI. Avoid routing high-speed signals (>50 MHz) under the PQFP body to limit crosstalk into the device's analog substrate.
Each EPM7128SQC160-15N user I/O can source/sink up to 25 mA DC and supports 5V TTL thresholds. When driving long PCB traces or cables, add a 33 Ξ© series resistor near the CPLD pin to dampen ringing. Inputs from noisy buses should be filtered with a 100 ns RC network or a Schmitt-trigger input buffer. Do not exceed the absolute maximum DC input voltage of 7V; undershoot below -2V for >100 mA / >20 ns is also prohibited.
Do not confuse the speed-grade suffix: -10 / -10N are faster than -15N. Note that VCC must rise monotonically for EPM7128A / EPM7256A devices only - this constraint does NOT apply to the non-A MAX 7000S EPM7128SQC160-15N. For ISP via JTAG, ensure TCK is not floating during board power-up; tie TCK to GND through a 10 kΞ© pull-down. Always re-verify the configuration after reflow because EEPROM retention is sensitive to thermal exposure above 150 Β°C.
The PQFP-160 package has a thermal resistance (ΞΈJA) of approximately 35-40 Β°C/W on a standard 4-layer PCB. The EPM7128SQC160-15N typically dissipates 0.5-1.5 W depending on toggle frequency and IO loading. Estimate: at full 76.9 MHz toggle with 100 I/Os at 20 pF each, ICC β 150-300 mA and P β 0.75-1.5 W, giving a junction rise of ~30-60 Β°C above ambient. Ensure ambient remains below 70 Β°C to keep Tj within the 125 Β°C commercial limit.
Compliance Information
RoHS, REACH, halogen-free, and conflict-minerals status are not explicitly stated in the verified web data; marked unknown. The N suffix indicates lead-free build. AEC-Q100 not applicable - this is a commercial-grade CPLD, not an automotive-qualified part.
