Altera

EPM9560RC208-3 - 560 Macrocell MAX 9000 EPLD | Intel / Altera

Référence : EPM9560RC208-3 ⚠ Dernier achat

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5V Vdss 208-pin RQFP (Power Quad Flat Pack) Package approximately 3 ns (slowest grade) Speed

À partir de $58.5 USD / unité

MOQ : 1 |

Prix mis à jour : 2026-09-13

Tarifs dégressifs

Qté	Prix unitaire	Total
1	$95	$95,00
10	$85.5	$855,00
100	$72	$7 200,00
500	$64	$32 000,00
1 000	$58.5	$58 500,00

ℹ️ Tous les prix sont en USD

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EPM9560RC208-3 Présentation

The Intel / Altera EPM9560RC208-3 is a high-density MAX 9000 family Erasable Programmable Logic Device (EPLD) delivering 560 macrocells and 12,000 usable gates in a 208-pin Power Quad Flat Pack (RQFP) package. Built on a 0.5 µm CMOS EPROM process, it integrates multiple Logic Array Blocks (LABs) with a Programmable Interconnect Array (PIA), providing designers with the largest device in the classic Altera MAX 9000 family for glue-logic, bus-interface, and state-machine integration.

A programmable logic device such as an EPLD is a non-volatile, in-system re-programmable integrated circuit that replaces dozens of discrete TTL/CMOS glue-logic ICs. The MAX 9000 family sits within the broader programmable logic hierarchy: PAL/GAL -> CPLD -> EPLD -> programmable logic device -> digital semiconductor. Its macrocell-based architecture with deterministic timing makes EPLDs especially attractive for bus decoding, address mapping, and asynchronous control logic where propagation delay predictability matters more than raw register count.

Key features include 560 macrocells, 16 Logic Array Blocks (LABs), a maximum operating frequency of , a pin-to-pin delay of approximately 3 ns (speed grade -3, the slowest of the -3/-10/-12/-15/-17/-20 series), and 5V tolerant I/O. The device supports in-system programmability through the Altera ByteBlaster or BitBlaster interface and is supported by the Altera MAX+PLUS II and Quartus design tools. Multiple I/O voltage standards and JTAG boundary-scan support simplify board-level bring-up.

Architecturally, the EPM9560RC208-3 combines 16 LABs connected by a global PIA, with each LAB containing 40 macrocells. Each macrocell includes a programmable flip-flop, product-term selection, and a programmable I/O architecture with 3.3V or 5V interfaces. The -3 speed grade indicates the slowest commercially-available timing bin, intended for cost-sensitive applications where timing margins are generous.

Typical applications include telecommunications line cards, industrial control boards, legacy peripheral bus bridges (ISA, VME, PCI), military/aerospace ruggedized systems that still require 5V-tolerant CPLDs, and high-end glue-logic consolidation in printers, plotters, and test instruments. Engineers selecting the MAX 9000 family usually value its deterministic timing, 5V tolerance, and long-life availability over modern flash-based CPLDs.

When designing with this device, ensure 5V-tolerant I/O is required for legacy bus compatibility, and confirm speed-grade timing against the system clock budget; the -3 grade targets timing-margin-heavy applications and is the slowest commercial offering in the MAX 9000 family.

This page synthesizes distributor pricing, drop-in same-package alternatives (EPM9560RC208-10, EPM9560RC208-15, EPM9560RC208-20 from the same family), lifecycle observations, and practical design notes not found in a single manufacturer datasheet.

Alternatives de remplacement direct pour EPM9560RC208-3 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.

Variantes de cette série

Modèles de la même série directement compatibles avec EPM9560RC208-3 (même facteur de forme et même empreinte) — différant par Package, Speed Grade, Device Type, Pin-to-Pin Delay (tPD), Usable Gates.

EPM9560RC208-10

Intel

Package: 208-pin RQFP (Plastic Quad Flat Pack)

Device Type: CPLD (Complex Programmable Logic Device)

Pin-to-Pin Delay (tPD): 10 ns