EPM9560WC208 - 560 Macrocell EE PLD MAX 9000 | Altera | CQFP-208
Référence : EPM9560WC208 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $185 | $185,00 |
| 10 | $168.5 | $1 685,00 |
| 100 | $152 | $15 200,00 |
| 500 | $138.25 | $69 125,00 |
| 1 000 | $125 | $125 000,00 |
EPM9560WC208 Présentation
The MAX 9000 family is a high-density complex programmable logic device (CPLD) lineage positioned between classic PAL/GAL arrays and modern FPGAs. It integrates multiple logic array blocks (LABs) with a programmable interconnect matrix (PIA), giving engineers thousands of usable flip-flops (the EPM9560 series reaches 772 flip-flops) on a single die. Designers choose this category when deterministic pin-to-pin timing, instant-on non-volatile configuration, and 5 V tolerance are all required - conditions that mainstream SRAM-based FPGAs cannot meet without external supervision.
Key features of the EPM9560WC208 include 560 macrocells across 35 LABs, 772 dedicated flip-flops, 16.6 ns pin-to-pin propagation delay in the -15 speed grade, in-system programmability via IEEE 1149.1 JTAG, and built-in hot-socketing support that allows the device to be inserted into a powered backplane without latch-up. The CQFP-208 ceramic package is a ruggedized form factor that historically served military, aerospace, and down-hole telemetry applications where plastic packages are unsuitable.
The architecture is built on a CMOS electrically erasable process; configuration EEPROM cells hold the pattern even when power is removed, eliminating the boot PROM required by SRAM FPGAs. With 149 I/O pins distributed across 5 V-tolerant banks, the EPM9560WC208 can bridge multiple logic domains on the same board, including 3.3 V microcontrollers, 5 V peripheral buses, and TTL peripherals, simplifying mixed-voltage glue logic.
Typical applications include military and aerospace avionics, industrial motor control, telecom backplane bridging, legacy bus protocol conversion (VME, PCI), and replacement of multiple discrete PAL/GAL devices. Engineers select the EPM9560WC208 when the design needs the instant-on behaviour of non-volatile EE memory combined with the timing predictability of a MAX-family CPLD.
When designing with this part, ensure that the JTAG chain is correctly ordered and that the ceramic CQFP-208 package is matched to a socket or PCB land pattern rated for ceramic body dimensions. Note that Altera has issued a Product Discontinuance Notice (PDN) for selected MAX 9000 ordering codes, so designers should verify lifecycle status and consider migrating to the EPM9560 in the 208-pin RQFP plastic package for new designs.
This page synthesizes distributor availability, drop-in alternatives, lifecycle status, and practical design notes not found in the manufacturer datasheet.
Alternatives de remplacement direct pour EPM9560WC208 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPM9560WC208 (même facteur de forme et même empreinte) — différant par Package, Device Type, Process Technology, User I/O Pins, Device Family.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPM9560RC208-15
✅ Remplacement direct✓ En stock
Contactez-nous pour le prix
Voir la fiche technique →EPM9560RC208-20
✅ Remplacement direct✓ En stock
Contactez-nous pour le prix
Voir la fiche technique →EPM9560RC208-10
✅ Remplacement direct✓ En stock
$15.4 / unité
Voir la fiche technique →EPM9560RC240-15
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$174.72 / unité
Voir la fiche technique →EPM9560ARC208-10
✅ Remplacement direct✓ En stock
Contactez-nous pour le prix
Voir la fiche technique →EPM9560WC208 Valeurs maximales et caractéristiques électriques
| Family | MAX 9000 |
| Device Type | EE Programmable Logic Device (CPLD) |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 35 |
| Flip-Flops | 772 |
| Maximum User I/O | 149 |
| Fréquence d'horloge maximale | 117.6 MHz |
| Propagation Delay (tpd, -15 grade) | 16.6 ns |
| Tension d'alimentation | 3.3 V or 5 V |
| Process Technology | CMOS, electrically erasable |
| Boîtier | 208-pin CQFP (Ceramic Quad Flat Pack) |
| Terminal Pitch | 0.50 mm |
| Type de montage | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG |
| Configuration Memory | Non-volatile EE (instant-on) |
| Hot Socketing Support | Yes |
Configuration des broches de EPM9560WC208
| Broche 1 | I/O — User I/O (bank A) |
| Broche 2 | I/O — User I/O (bank A) |
| Broche 3 | I/O — User I/O (bank A) |
| Broche 4 | I/O — User I/O (bank A) |
| Broche 5 | VCCINT — Core supply voltage (3.3 V or 5 V) |
| Broche 6 | I/O — User I/O (bank A) |
| Broche 7 | I/O — User I/O (bank A) |
| Broche 8 | I/O — User I/O (bank A) |
| Broche 9 | GND — Ground |
| Broche 10 | I/O — User I/O (bank A) |
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| Broche 21 | GND — Ground |
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| Broche 36 | I/O — User I/O (bank A) |
| Broche 37 | VCCIO — I/O supply voltage (3.3 V or 5 V) |
| Broche 38 | GND — Ground |
| Broche 39 | I/O — User I/O (bank A) |
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| Broche 61 | VCCINT — Core supply voltage (3.3 V or 5 V) |
| Broche 62 | I/O — User I/O (bank A) |
| Broche 63 | I/O — User I/O (bank A) |
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| Broche 78 | GND — Ground |
| Broche 79 | I/O — User I/O (bank A) |
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| Broche 97 | I/O — User I/O (bank A) |
| Broche 98 | VCCIO — I/O supply voltage (3.3 V or 5 V) |
| Broche 99 | GND — Ground |
| Broche 100 | I/O — User I/O (bank A) |
| Broche 101 | I/O — User I/O (bank A) |
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| Broche 120 | I/O — User I/O (bank A) |
| Broche 121 | GND — Ground |
| Broche 122 | I/O — User I/O (bank A) |
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| Broche 135 | I/O — User I/O (bank A) |
| Broche 136 | I/O — User I/O (bank A) |
| Broche 137 | VCCINT — Core supply voltage (3.3 V or 5 V) |
| Broche 138 | I/O — User I/O (bank A) |
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| Broche 153 | I/O — User I/O (bank A) |
| Broche 154 | I/O — User I/O (bank A) |
| Broche 155 | GND — Ground |
| Broche 156 | I/O — User I/O (bank A) |
| Broche 157 | I/O — User I/O (bank A) |
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| Broche 172 | I/O — User I/O (bank A) |
| Broche 173 | I/O — User I/O (bank A) |
| Broche 174 | VCCIO — I/O supply voltage (3.3 V or 5 V) |
| Broche 175 | GND — Ground |
| Broche 176 | I/O — User I/O (bank A) |
| Broche 177 | I/O — User I/O (bank A) |
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| Broche 189 | I/O — User I/O (bank A) |
| Broche 190 | I/O — User I/O (bank A) |
| Broche 191 | I/O — User I/O (bank A) |
| Broche 192 | I/O — User I/O (bank A) |
| Broche 193 | TDI — JTAG Test Data In (dedicated) |
| Broche 194 | TMS — JTAG Test Mode Select (dedicated) |
| Broche 195 | TCK — JTAG Test Clock (dedicated) |
| Broche 196 | GND — Ground |
| Broche 197 | TDO — JTAG Test Data Out (dedicated) |
| Broche 198 | I/O — User I/O (bank A) |
| Broche 199 | I/O — User I/O (bank A) |
| Broche 200 | I/O — User I/O (bank A) |
| Broche 201 | GND — Ground |
| Broche 202 | I/O — User I/O (bank A) |
| Broche 203 | I/O — User I/O (bank A) |
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| Broche 207 | I/O — User I/O (bank A) |
| Broche 208 | I/O — User I/O (bank A) |
Applications typiques
EPM9560WC208 convient pour 6 applications: Military and Aerospace Avionics, Legacy VME/PCI Bus Bridge, Industrial Motor Control, Telecom Backplane Glue Logic, Replacement of Multiple Discrete PAL/GAL Devices, High-Reliability Test and Measurement.
Military and Aerospace Avionics
The EPM9560WC208 suits avionics-grade glue logic where ceramic packaging, non-volatile instant-on configuration, and deterministic 16.6 ns pin-to-pin timing are mandatory. Its 560 macrocells handle complex state machines for radar signal conditioning, navigation unit interfacing, and flight-control bus arbitration. With 149 user I/O, the device bridges multiple 5 V and 3.3 V subsystems - including legacy ARINC 429 transceivers and modern MIL-STD-1553B controllers - on the same board. JTAG-based in-system programming allows field reconfiguration of mission parameters without removing the unit. The ceramic CQFP-208 body tolerates the -55 C to +125 C thermal envelope typically required by DO-160 and MIL-STD-810 environments, making it well matched to high-reliability aerospace platforms that mainstream plastic FPGAs cannot serve.
Recommandé
Legacy VME/PCI Bus Bridge
The EPM9560WC208 functions as a deterministic bridge between legacy VMEbus, PCI, and CompactPCI peripherals and modern processors. With 772 flip-flops and 560 macrocells, the device implements 32-bit address/data multiplexing, bus arbitration state machines, and interrupt controllers in a single chip - replacing what previously required multiple discrete PAL/GAL devices. The 16.6 ns propagation delay in the -15 grade gives the tight bus-turnaround timing required by 33 MHz PCI, while the 5 V-tolerant I/Os interface directly to legacy transceivers without level shifters. Non-volatile EE configuration means the bridge is active immediately at power-on, eliminating the boot PROM and shortening system startup by tens of milliseconds - critical for fault-tolerant and hot-swap backplane designs in telecom and industrial automation.
Recommandé
Industrial Motor Control
The EPM9560WC208 drives the deterministic glue logic at the heart of AC induction, BLDC, and servo motor controllers. Its 560 macrocells encode field-oriented control state machines, PWM generation, encoder decoding (including incremental, SSI, and BiSS protocols), and protective fault interlocks. The 117.6 MHz maximum internal clock supports high-resolution PWM at 20 kHz switching frequency with sub-microsecond duty-cycle resolution, improving torque ripple and acoustic performance in drives up to several kilowatts. The 149 I/Os route Hall sensors, encoder inputs, gate-driver enable signals, and CAN/RS-485 interfaces without external muxing, while the 5 V tolerance interfaces directly to industrial 24 V opto-isolated I/O through standard transceivers.
Recommandé
Telecom Backplane Glue Logic
The EPM9560WC208 is a strong fit for telecom backplane glue logic that must hot-swap into a powered shelf without disturbing the bus. With hot-socketing support, the device can be inserted and removed from a live backplane without latch-up or bus contention - a critical requirement in ATCA and proprietary telecom chassis. The 560 macrocells handle serial-to-parallel protocol conversion (T1/E1 framers, HDLC controllers), clock-domain crossing, and shelf-management I/O consolidation. Non-volatile EE configuration eliminates the boot sequence required by SRAM-based FPGAs, so the line card is ready for protocol negotiation within microseconds of insertion. 5 V and 3.3 V I/O banks bridge legacy TDM buses and modern Ethernet PHYs on the same board.
Recommandé
Replacement of Multiple Discrete PAL/GAL Devices
Engineers frequently select the EPM9560WC208 to consolidate dozens of legacy 22V10, 20V8, and 16V8 GAL devices onto a single chip. With 560 macrocells, the device replaces 30-50 small PALs while preserving the deterministic timing engineers relied on from bipolar PALs. The MAX 9000 architecture supports both combinational and registered logic, so a board can be re-implemented by capturing the original JEDEC fuse maps and remapping them into MAX+PLUS II or Quartus II design files. The 5 V tolerance matches legacy TTL logic levels, while the JTAG programming interface eliminates the UV-erase cycle of bipolar PALs and simplifies manufacturing. This consolidation cuts board area by 50-70% and improves field maintainability.
Recommandé
High-Reliability Test and Measurement
The EPM9560WC208 is used as deterministic timing and pattern-generation logic in ATE, oscilloscope, and spectrum-analyzer front-ends. Its 16.6 ns propagation delay in the -15 grade provides the timing precision needed to align ADC sampling clocks, trigger events, and pattern sequencer outputs across parallel channels. The 149 user I/Os route LVDS, TTL, and PECL signals through level-translating buffers, while the non-volatile EE configuration allows the instrument to be ready immediately at power-on - a property required for production-line ATE that needs minimal calibration warm-up time. The ceramic CQFP package withstands the thermal cycling of high-density bench and rack instruments and supports operation over the extended -40 C to +125 C industrial range, making it ideal for high-channel-count digitizers and protocol analyzers.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPM9560WC208 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPM9560RC208-15 | EPM9560RC208-20 | EPM9560RC208-10 | EPM9560RC240-15 | EPM9560ARC208-10 |
|---|---|---|---|---|---|---|
| Package | 208-pin CQFP (ceramic) | 208-pin RQFP (plastic) | 208-pin RQFP (plastic) | 208-pin RQFP (plastic) | 240-pin RQFP (plastic) | 208-pin RQFP (plastic, military temp) |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 |
| Maximum User I/O | 149 | 149 | 149 | 149 | 165 | 149 |
| Speed Grade (tpd) | -15 (16.6 ns) | -15 (16.6 ns) | -20 (slower tpd) | -10 (faster tpd) | -15 (16.6 ns) | -10 (faster tpd) |
| Supply Voltage | 3.3 V or 5 V | 3.3 V or 5 V | 3.3 V or 5 V | 3.3 V or 5 V | 3.3 V or 5 V | 3.3 V or 5 V |
| Lifecycle Status | NRND (CQFP variant discontinued) | Active (RQFP replacement) | Active (RQFP replacement) | Active (RQFP replacement) | Active (RQFP replacement) | Limited (military variant) |
| Configuration Memory | Non-volatile EE (instant-on) | Non-volatile EE (instant-on) | Non-volatile EE (instant-on) | Non-volatile EE (instant-on) | Non-volatile EE (instant-on) | Non-volatile EE (instant-on) |
| JTAG Programming | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) |
| Pin Count | 208 | 208 | 208 | 208 | 240 | 208 |
Principaux différenciateurs
- Largest macrocell count in MAX 9000 family (vs EPM9480RC208-15)
- Ceramic CQFP package for ruggedized applications (vs EPM9560RC208-15)
- Non-volatile EE instant-on configuration (vs EPM7512BQC208-7 (MAX 7000))
Notes de conception
Estimated: The EPM9560WC208 (CQFP-208 ceramic) is listed on the Altera/Intel Product Discontinuance Notice for selected MAX 9000 ordering codes retrieved on 2026-09-13. Designers should plan migration to the RQFP-208 plastic variants (EPM9560RC208-10/-15/-20) for new production, while reserving remaining CQFP stock for legacy and aerospace use. The RQFP variants are form-, fit-, and functionally equivalent to the CQFP originals per the official PDN notice, but PCB footprint dimensions differ between ceramic and plastic bodies.
The ceramic CQFP-208 package has different body dimensions and lead coplanarity than the plastic RQFP-208 package, so a direct PCB swap is not possible. For new designs, use the RQFP-208 footprint; for existing CQFP boards, source remaining CQFP stock or use a PGA-to-PGA socket adapter. Decoupling should include 0.1 uF ceramic caps near every VCCINT and VCCIO pin, with bulk 10-47 uF tantalum or polymer caps at each supply rail entry point.
Estimated: With 149 user I/Os and a 117.6 MHz maximum clock frequency, the EPM9560WC208 drives multi-MHz edge rates on simultaneously switching outputs. Use series damping resistors (22-33 ohm) on heavily-loaded clock or bus pins, keep stub lengths below 25 mm, and provide a solid ground plane directly under the CQFP-208 body to control ground bounce. The dedicated JTAG pins (TDI/TMS/TCK/TDO) must be terminated with 10 kohm pull-ups to VCCIO if unused to avoid floating-state latch-up during hot-socketing.
Informations de conformité
Ceramic CQFP-208 package with MIL/aerospace heritage; RoHS and REACH compliance not confirmed in available datasheets. Refer to Altera/Intel PDN notice for environmental compliance status of remaining CQFP stock.
