STM32H755ZIT6 - Dual-Core Cortex-M7/M4 MCU, 2MB Flash | STMicroelectronics
Référence : STM32H755ZIT6 ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $25.3 | $25,30 |
| 10 | $22.77 | $227,70 |
| 100 | $20.24 | $2 024,00 |
| 500 | $18.22 | $9 110,00 |
| 1 000 | $16.19 | $16 190,00 |
STM32H755ZIT6 Présentation
A microcontroller (MCU) is a compact integrated circuit that combines a processor core, on-chip memory (flash and SRAM), and programmable peripherals used to govern a specific operation in an embedded system. The STM32H755ZIT6 belongs to the STM32H7 family, which sits at the top of the ST Cortex-M portfolio between the mainstream STM32F4/F7 lines and the lower-power STM32L4/U5 lines. Its dual-core architecture enables one core to handle time-critical control while the other runs communication stacks, GUI rendering, or machine-learning inference, with shared access to peripherals through a bus-matrix arbitration scheme.
Key differentiating features include the 480 MHz Cortex-M7 with double-precision FPU and L1 cache, the 240 MHz Cortex-M4 with single-precision FPU, 2 MB flash with read-while-write support, 1 MB SRAM split across DTCM, AXI SRAM and SRAM1/2/3 domains, and an integrated SMPS step-down converter for high-efficiency core supply. The device exposes 114 GPIO, 35 communication interfaces (including Ethernet, USB OTG HS/FS, CAN FD, SPI, I2C, UART, SDMMC), three 16-bit ADCs up to 3.6 MSPS, two 12-bit DACs, two SAI for audio, an LCD-TFT controller, a JPEG codec, and a crypto/hash suite compliant with AES, SHA and RSA.
Built on a 40 nm low-power CMOS process, the part operates from 1.62 V to 3.6 V on VDD and supports an industrial -40 °C to +85 °C temperature range. The dual-bank flash with read-while-write capability simplifies in-field firmware upgrades and A/B partition schemes, while the Chrom-ART accelerator offloads 2D drawing to free the Cortex-M7 for application code. The integrated SMPS reduces core current draw by roughly 30% compared to an external LDO-only supply, easing thermal design in compact enclosures.
Typical applications include industrial HMI panels with TFT LCD, motor-control inverter boards, smart-home gateways, audio DSP front-ends with SAI-to-DAC chains, vision-based edge-AI nodes using the JPEG codec, and medical instrumentation requiring deterministic USB or Ethernet connectivity. The dual-core topology is especially valuable when a real-time control loop must coexist with a Linux-like user interface stack on the same die.
When designing with this device, treat the SMPS inductor selection as critical because ripple directly couples into the core logic rail. Provide a 4.7 µF input bulk plus 100 nF + 1 µF ceramic decoupling near each VDD pin, and follow the ST reference layout for the 240 MHz M7 traces to avoid signal-integrity issues. Boot pins BOOT0 and the option-byte bank must be configured before each power cycle, otherwise the part may revert to system memory bootloader.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on the ST product page alone.
Alternatives de remplacement direct pour STM32H755ZIT6 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec STM32H755ZIT6 (même facteur de forme et même empreinte) — différant par Communication Interfaces, Package, Operating Temperature, ADC, SRAM.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
STM32H755BIT6
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
STM32H745BIT6
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
STM32H745IIK6
✅ Remplacement direct✓ En stock
$12.6 / unité
Voir la fiche technique →STM32H745IIT6
✅ Remplacement direct✓ En stock
$10.62 / unité
Voir la fiche technique →STM32H753IIT6
✅ Remplacement direct✓ En stock
$9.45 / unité
Voir la fiche technique →STM32H755ZIT6 Valeurs maximales et caractéristiques électriques
| Core Architecture | Dual-core Arm Cortex-M7 + Cortex-M4 |
| Cortex-M7 Max Frequency | 480 MHz |
| Cortex-M4 Max Frequency | 240 MHz |
| Flash Memory | 2 MB (dual-bank) |
| SRAM | 1 MB (DTCM + AXI + SRAM1/2/3) |
| Boîtier | LQFP-144 (20x20 mm) |
| GPIO Count | 114 |
| Supply Voltage VDD | 1.62 V to 3.6 V |
| Température de fonctionnement | -40 °C to +85 °C (industrial grade) |
| ADC | 3 x 16-bit, up to 3.6 MSPS |
| DAC | 2 x 12-bit |
| Communication Interfaces | Ethernet, USB OTG HS/FS, 2x CAN FD, 6x SPI, 4x I2C, USART/UART, SDMMC, SAI |
| Graphics | Chrom-ART Accelerator, LCD-TFT controller, JPEG codec |
| Crypto Accelerators | AES, SHA, RSA, TRNG |
| Internal SMPS | Yes (step-down for core) |
| Process Node | 40 nm CMOS |
| Type de montage | Surface Mount |
| Niveau MSL | 3 (per JEDEC J-STD-020) |
| Statut RoHS | Compliant |
Configuration des broches de STM32H755ZIT6
| Broche 1 | PE02 — GPIO PE2, alternate function I/O |
| Broche 2 | PE03 — GPIO PE3, alternate function I/O |
| Broche 3 | PE04 — GPIO PE4, alternate function I/O |
| Broche 4 | PE05 — GPIO PE5, alternate function I/O |
| Broche 5 | PE06 — GPIO PE6, alternate function I/O |
| Broche 6 | VBAT — Backup battery supply input |
| Broche 7 | PC13 — GPIO PC13, tamper-RTC |
| Broche 8 | PC14 — GPIO PC14, OSC32_IN |
| Broche 9 | PC15 — GPIO PC15, OSC32_OUT |
| Broche 10 | VSS — Ground reference |
| Broche 11 | VDD — Digital supply 1.62-3.6 V |
| Broche 12 | VSS — Ground reference |
| Broche 13 | VDD — Digital supply 1.62-3.6 V |
| Broche 14 | OSC_IN — HSE oscillator input |
| Broche 15 | OSC_OUT — HSE oscillator output |
| Broche 16 | NRST — Reset input, active low |
| Broche 17 | VREF+ — ADC positive reference |
| Broche 18 | PA00 — GPIO PA0, WKUP/ADC_IN |
| Broche 19 | PA01 — GPIO PA1, ADC_IN |
| Broche 20 | PA02 — GPIO PA2, alternate function I/O |
| Broche 21 | PA03 — GPIO PA3, alternate function I/O |
| Broche 22 | VSS — Ground reference |
| Broche 23 | VDD — Digital supply 1.62-3.6 V |
| Broche 24 | PA04 — GPIO PA4, DAC_OUT1 |
| Broche 25 | PA05 — GPIO PA5, DAC_OUT2 |
| Broche 26 | PA06 — GPIO PA6, alternate function I/O |
| Broche 27 | PA07 — GPIO PA7, alternate function I/O |
| Broche 28 | PB00 — GPIO PB0, alternate function I/O |
| Broche 29 | PB01 — GPIO PB1, alternate function I/O |
| Broche 30 | PB02 — GPIO PB2, BOOT1 |
| Broche 31 | PE07 — GPIO PE7, alternate function I/O |
| Broche 32 | PE08 — GPIO PE8, alternate function I/O |
| Broche 33 | PE09 — GPIO PE9, alternate function I/O |
| Broche 34 | PE10 — GPIO PE10, alternate function I/O |
| Broche 35 | PE11 — GPIO PE11, alternate function I/O |
| Broche 36 | PE12 — GPIO PE12, alternate function I/O |
| Broche 37 | PE13 — GPIO PE13, alternate function I/O |
| Broche 38 | PE14 — GPIO PE14, alternate function I/O |
| Broche 39 | PE15 — GPIO PE15, alternate function I/O |
| Broche 40 | PB10 — GPIO PB10, I2C2_SCL |
| Broche 41 | PB11 — GPIO PB11, I2C2_SDA |
| Broche 42 | VCAP — Core voltage decoupling cap |
| Broche 43 | VSS — Ground reference |
| Broche 44 | VDD — Digital supply 1.62-3.6 V |
| Broche 45 | PB12 — GPIO PB12, alternate function I/O |
| Broche 46 | PB13 — GPIO PB13, alternate function I/O |
| Broche 47 | PB14 — GPIO PB14, alternate function I/O |
| Broche 48 | PB15 — GPIO PB15, alternate function I/O |
| Broche 49 | PD08 — GPIO PD8, alternate function I/O |
| Broche 50 | PD09 — GPIO PD9, alternate function I/O |
| Broche 51 | PD10 — GPIO PD10, alternate function I/O |
| Broche 52 | PD11 — GPIO PD11, alternate function I/O |
| Broche 53 | PD12 — GPIO PD12, alternate function I/O |
| Broche 54 | PD13 — GPIO PD13, alternate function I/O |
| Broche 55 | VSS — Ground reference |
| Broche 56 | VDD — Digital supply 1.62-3.6 V |
| Broche 57 | PD14 — GPIO PD14, alternate function I/O |
| Broche 58 | PD15 — GPIO PD15, alternate function I/O |
| Broche 59 | PC06 — GPIO PC6, alternate function I/O |
| Broche 60 | PC07 — GPIO PC7, alternate function I/O |
| Broche 61 | PC08 — GPIO PC8, alternate function I/O |
| Broche 62 | PC09 — GPIO PC9, alternate function I/O |
| Broche 63 | PA08 — GPIO PA8, alternate function I/O |
| Broche 64 | PA09 — GPIO PA9, USART1_TX |
| Broche 65 | PA10 — GPIO PA10, USART1_RX |
| Broche 66 | PA11 — GPIO PA11, USB OTG D- |
| Broche 67 | PA12 — GPIO PA12, USB OTG D+ |
| Broche 68 | PA13 — GPIO PA13, SWDIO |
| Broche 69 | VCAP — Core voltage decoupling cap |
| Broche 70 | VSS — Ground reference |
| Broche 71 | VDD — Digital supply 1.62-3.6 V |
| Broche 72 | PA14 — GPIO PA14, SWCLK |
| Broche 73 | PA15 — GPIO PA15, JTDI |
| Broche 74 | PC10 — GPIO PC10, alternate function I/O |
| Broche 75 | PC11 — GPIO PC11, alternate function I/O |
| Broche 76 | PC12 — GPIO PC12, alternate function I/O |
| Broche 77 | PD00 — GPIO PD0, alternate function I/O |
| Broche 78 | PD01 — GPIO PD1, alternate function I/O |
| Broche 79 | PD02 — GPIO PD2, alternate function I/O |
| Broche 80 | PD03 — GPIO PD3, alternate function I/O |
| Broche 81 | PD04 — GPIO PD4, alternate function I/O |
| Broche 82 | PD05 — GPIO PD5, alternate function I/O |
| Broche 83 | PD06 — GPIO PD6, alternate function I/O |
| Broche 84 | PD07 — GPIO PD7, alternate function I/O |
| Broche 85 | PB03 — GPIO PB3, JTDO/TRACESWO |
| Broche 86 | PB04 — GPIO PB4, NJTRST |
| Broche 87 | PB05 — GPIO PB5, alternate function I/O |
| Broche 88 | PB06 — GPIO PB6, alternate function I/O |
| Broche 89 | PB07 — GPIO PB7, alternate function I/O |
| Broche 90 | PB08 — GPIO PB8, alternate function I/O |
| Broche 91 | PB09 — GPIO PB9, I2C1_SDA |
| Broche 92 | PE00 — GPIO PE0, alternate function I/O |
| Broche 93 | PE01 — GPIO PE1, alternate function I/O |
| Broche 94 | VSS — Ground reference |
| Broche 95 | VDD — Digital supply 1.62-3.6 V |
| Broche 96 | VSS — Ground reference |
| Broche 97 | VDD — Digital supply 1.62-3.6 V |
| Broche 98 | PI00 — GPIO PI0, alternate function I/O |
| Broche 99 | PI01 — GPIO PI1, alternate function I/O |
| Broche 100 | PI02 — GPIO PI2, alternate function I/O |
| Broche 101 | PI03 — GPIO PI3, alternate function I/O |
| Broche 102 | VSS — Ground reference |
| Broche 103 | VDD — Digital supply 1.62-3.6 V |
| Broche 104 | PA15 — GPIO PA15, alternate function I/O |
| Broche 105 | PI04 — GPIO PI4, alternate function I/O |
| Broche 106 | PI05 — GPIO PI5, alternate function I/O |
| Broche 107 | PI06 — GPIO PI6, alternate function I/O |
| Broche 108 | PI07 — GPIO PI7, alternate function I/O |
| Broche 109 | PG00 — GPIO PG0, alternate function I/O |
| Broche 110 | PG01 — GPIO PG1, alternate function I/O |
| Broche 111 | PG02 — GPIO PG2, alternate function I/O |
| Broche 112 | PG03 — GPIO PG3, alternate function I/O |
| Broche 113 | PG04 — GPIO PG4, alternate function I/O |
| Broche 114 | PG05 — GPIO PG5, alternate function I/O |
| Broche 115 | PG06 — GPIO PG6, alternate function I/O |
| Broche 116 | PG07 — GPIO PG7, alternate function I/O |
| Broche 117 | PG08 — GPIO PG8, alternate function I/O |
| Broche 118 | VSS — Ground reference |
| Broche 119 | VDD — Digital supply 1.62-3.6 V |
| Broche 120 | PC00 — GPIO PC0, ADC_IN10 |
| Broche 121 | PC01 — GPIO PC1, ADC_IN11 |
| Broche 122 | PC02 — GPIO PC2, ADC_IN12 |
| Broche 123 | PC03 — GPIO PC3, ADC_IN13 |
| Broche 124 | PF00 — GPIO PF0, alternate function I/O |
| Broche 125 | PF01 — GPIO PF1, alternate function I/O |
| Broche 126 | PF02 — GPIO PF2, alternate function I/O |
| Broche 127 | PF03 — GPIO PF3, alternate function I/O |
| Broche 128 | PF04 — GPIO PF4, alternate function I/O |
| Broche 129 | PF05 — GPIO PF5, alternate function I/O |
| Broche 130 | VSS — Ground reference |
| Broche 131 | VDD — Digital supply 1.62-3.6 V |
| Broche 132 | PF06 — GPIO PF6, alternate function I/O |
| Broche 133 | PF07 — GPIO PF7, alternate function I/O |
| Broche 134 | PF08 — GPIO PF8, alternate function I/O |
| Broche 135 | PF09 — GPIO PF9, alternate function I/O |
| Broche 136 | PF10 — GPIO PF10, alternate function I/O |
| Broche 137 | PH00 — GPIO PH0, alternate function I/O |
| Broche 138 | PH01 — GPIO PH1, alternate function I/O |
| Broche 139 | VSS — Ground reference |
| Broche 140 | VDD — Digital supply 1.62-3.6 V |
| Broche 141 | PB03 — GPIO PB3, alternate function I/O |
| Broche 142 | PB04 — GPIO PB4, alternate function I/O |
| Broche 143 | PB05 — GPIO PB5, alternate function I/O |
| Broche 144 | VSS — Ground reference |
Applications typiques
STM32H755ZIT6 convient pour 6 applications: Industrial HMI with TFT LCD, Motor Control and Field-Oriented Control (FOC), Edge-AI Vision and Audio DSP, Audio Processing and USB Audio Interfaces, Smart Home Gateway and IoT Hub, Medical Instrumentation and Patient Monitoring.
Industrial HMI with TFT LCD
The STM32H755ZIT6 is well-suited for industrial HMI panels because the 480 MHz Cortex-M7 drives the LCD-TFT controller and Chrom-ART accelerator while the 240 MHz Cortex-M4 manages touch scanning, communication stacks and real-time housekeeping. With 1 MB of SRAM spread across DTCM and AXI banks, the chip supports 800x480 framebuffers in RGB565 without external SDRAM. Compared with single-core STM32H743 designs, the 755's M4 offload keeps touch latency under 10 ms even during complex UI redraws.
Recommandé
Motor Control and Field-Oriented Control (FOC)
Industrial motor drives benefit from the STM32H755ZIT6's dual-core architecture: the Cortex-M4 executes the FOC control loop at deterministic 20 kHz while the Cortex-M7 handles state estimators, sensor fusion and EtherCAT/CAN FD communication. The three 16-bit ADCs sample phase currents synchronously at up to 3.6 MSPS, providing the bandwidth needed for high-RPM PMSM control. The integrated SMPS keeps the core draw under 200 mA even at full M7+M4 load, simplifying thermal design in compact inverter enclosures.
Recommandé
Edge-AI Vision and Audio DSP
Edge-AI vision and audio nodes leverage the STM32H755ZIT6's M7 vector DSP instructions (single-precision FPU + DSP extensions) to run quantized neural networks at the edge. The M4 manages microphone array sampling and PDM-to-PCM conversion through SAI while the M7 runs keyword spotting or person-detection inference on the JPEG-decoded camera frame. Hardware AES/SHA offloads secure OTA updates, and the 1 MB SRAM holds both the model weights and live audio buffers without external PSRAM.
Recommandé
Audio Processing and USB Audio Interfaces
USB audio interfaces and professional DAC/ADC peripherals benefit from the STM32H755ZIT6's two SAI interfaces, USB OTG HS/FS with PHY, and 480 MHz M7 core for real-time DSP. The M7 runs mixing, EQ and reverb while the M4 handles USB audio class 2.0 enumeration and HID control surface polling. AES-256 hardware acceleration secures studio-grade audio firmware against tampering, and 1 MB SRAM provides buffer headroom for 8-channel 24-bit/96 kHz streams.
Recommandé
Smart Home Gateway and IoT Hub
Smart home gateways need simultaneous Ethernet, Wi-Fi coexistence, Zigbee/Thread radio handling and cloud TLS - all of which the STM32H755ZIT6 manages via dual cores. The M7 runs the TLS 1.3 stack and MQTT broker logic with hardware AES/SHA acceleration, while the M4 polls the SAI/SDMMC and drives user-facing LEDs and buttons. The integrated SMPS keeps idle power below 50 mA even with both cores clocked at their respective maxima, satisfying always-on IoT power budgets.
Recommandé
Medical Instrumentation and Patient Monitoring
Patient monitors and laboratory analyzers require deterministic USB or Ethernet data transfer alongside signal processing - exactly the dual-core workload the STM32H755ZIT6 was designed for. The M7 runs FFT and filter pipelines on ECG/EEG streams sampled by the 16-bit ADCs, while the M4 manages the USB device stack, LCD-TFT display and alarm logic. Hardware crypto satisfies FDA cybersecurity guidance for medical devices, and the LQFP-144 package supports conventional PCB assembly for medium-volume production.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour STM32H755ZIT6 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | STM32H755BIT6 | STM32H745BIT6 | STM32H745IIK6 | STM32H745IIT6 | STM32H753IIT6 |
|---|---|---|---|---|---|---|
| Brand | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics |
| Package | LQFP-144 (20x20 mm) | LQFP-144 - same | LQFP-144 - same | LQFP-176 (24x24 mm) - different | LQFP-176 (24x24 mm) - different | LQFP-176 (24x24 mm) - different |
| Core Architecture | Dual M7 480 MHz + M4 240 MHz | Dual M7 + M4 - same | Dual M7 + M4 - same | Dual M7 + M4 - same | Dual M7 + M4 - same | Single M7 480 MHz only |
| Flash Memory | 2 MB | 1 MB (-50%) | 1 MB (-50%) | 2 MB | 2 MB | 2 MB |
| SRAM | 1 MB | 1 MB - same | 1 MB - same | 1 MB - same | 1 MB - same | 1 MB - same |
| Hardware Crypto (AES/SHA/RSA) | Yes | Yes | No | No | No | Yes |
| GPIO Count | 114 | 114 | 114 | 140 (LQFP-176) | 140 (LQFP-176) | 140 (LQFP-176) |
Principaux différenciateurs
- Only STM32H755 line member with hardware crypto accelerator on LQFP-144 (vs STM32H745BIT6)
- Dual-core topology enables deterministic real-time task partitioning (vs STM32H743IIT6 (LQFP-176))
- LQFP-144 land pattern supports conventional PCB assembly (vs STM32H753XIH6 (TFBGA-176))
Notes de conception
The STM32H755ZIT6 integrates a step-down SMPS for the core logic rail, but its inductor selection is critical: ST recommends a 4.7 µH shielded inductor with 30 mΩ DCR or better and a 4.7 µF X7R input plus 22 µF output capacitor. Inadequate inductor ripple will couple into the core VDD, causing the M7 to throttle or triggering spurious resets under heavy DSP load. Place the inductor within 10 mm of the VLX pin and keep its switched loop area under 25 mm².
Route the 480 MHz Cortex-M7 high-speed traces (SDMMC, SAI, SPI, Ethernet RMII) with impedance-controlled 50 Ω microstrips over a continuous ground plane, and place a 100 nF plus 1 µF ceramic decoupling pair within 5 mm of every VDD/VSS pair. For LQFP-144 routing, fan out the inner-row GPIO on both top and inner layers using vias-in-pad to escape the 0.5 mm pitch without violating DRC. Verify all crystal traces (HSE and LSE) are under 10 mm with ground shielding on both sides.
Dual-core 480 MHz operation can dissipate 500 mW to 800 mW, which is meaningful in a sealed enclosure. Estimated: at 480 MHz M7 + 240 MHz M4 with both cores 80% utilized, VDD=3.3 V and Tj=85 °C max, a minimum copper-pour area of approximately 600 mm² on a 4-layer 1 oz PCB is required to stay within thermal limits. Add thermal vias under the exposed pad region if migrating to the TFBGA variant.
The BOOT0 pin state at reset determines the boot source (user flash, system memory bootloader, or SRAM); leaving BOOT0 floating causes intermittent boot failures. Always strap BOOT0 with a 10 kΩ pull-down for normal operation or 10 kΩ pull-up to enter bootloader. Also configure the option bytes in the OB program before locking, because locking them with wrong values can brick the part until an external SWD programmer unlocks the RDP level.
Informations de conformité
RoHS and REACH compliant per ST product page. Not AEC-Q100 qualified - STM32H755ZIT6 is industrial grade (-40 to +85 C). For automotive AEC-Q100 designs, use STM32H755ZIT6Q or migrate to STM32H7S automotive variants.