EP3SL200H780C3N vs EP3SL200H780I4LN तुलना
विस्तृत दोनों ओर की तुलना EP3SL200H780C3N द्वारा Intel और EP3SL200H780I4LN द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP3SL200H780C3N | EP3SL200H780I4LN |
|---|---|---|
| ब्रांड | Intel | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | NRND | NRND |
| Family | Stratix III L (low-power) | Stratix III L (Low-Power) |
| Process Node | 40 nm | — |
| Logic Elements | 200,000 | — |
| Embedded Memory Bits | 10,901,504 bits | — |
| Logic Array Blocks (LABs) | 8,000 | — |
| User I/Os | 488 | — |
| पैकेज | 780-Ball FCBGA (HBGA), 29 x 29 mm | — |
| माउंटिंग प्रकार | Surface Mount | Surface Mount |
| Maximum Internal Clock Frequency | 800 MHz | — |
| Transceivers | 24 channels, up to 3.75 Gbps | — |
| DSP Blocks | 384 | — |
| Speed Grade | C3 (commercial, -3 speed) | I4 (Industrial, mid-speed grade) |
| ऑपरेटिंग तापमान | 0C to +85C (commercial) | -40C to +100C (industrial) |
| Voltage - Core | 0.9 V / 1.0 V (core, VCC) | — |
| Voltage - I/O | 1.2 V to 3.3 V (VCCIO banks) | — |
| MSL स्तर | 3 | MSL 3 (168 Hours, per JEDEC J-STD-020) |
| Lead-Free / RoHS | Yes | — |
| Mounting Pitch | 1.0 mm ball pitch | — |
| PLLs | 12 (Stratix III PLL array) | — |
| Configuration | JTAG IEEE Std 1149.1, passive/active serial | — |
| Series | — | Stratix III L |
| Manufacturer | — | Intel / Altera (now Intel PSG) |
| Number of Logic Elements / Cells | — | 200,000 |
| Number of LABs / CLBs | — | 8,000 |
| Total RAM Bits | — | 10,901,504 (approximately 10.9 Mbit) |
| Number of I/O | — | 488 |
| Voltage - Supply | — | 0.9 V core (selectable Vcore) |
| पैकेज / केस | — | 780-BBGA, FCBGA (Flip-Chip BGA) |
| Process Technology | — | 65 nm CMOS |
| RoHS स्थिति | — | RoHS Compliant (lead-free) |
| Roaming Pin Name Suffix | — | LN = lead-free, industrial temp, H780 780-ball package |