EP1810LC-30 vs EP1810LC-25 Perbandingan
Perbandingan bersamaan detil EP1810LC-30 dari Altera dan EP1810LC-25 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP1810LC-30 | EP1810LC-25 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | — |
| Macrocells | 48 | 48 |
| Flip-Flops | 48 (one per macrocell) | — |
| Speed Grade (tPD) | 30 ns | — |
| Tegangan Pemuat | 5 V (typical) | — |
| Technology | CMOS, low-power (LC) | CMOS EPLD (erasable programmable logic device) |
| Paket | JLCC-68 (68-pin J-Lead ceramic chip carrier) | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Programming | Device programmer or JTAG | — |
| Suhu Kerja | [DATA_NEEDED: temperature grade] | [DATA_NEEDED: temperature grade for LC package] |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| Jumlah Pin | 68 | — |
| Number of I/O Pins | [DATA_NEEDED: I/O count] | — |
| Logic Blocks | 48 macrocells | — |
| Status RoHS | unknown (legacy ceramic package) | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] |
| Product Family | — | Altera Classic EPLD |
| Part Number | — | EP1810LC-25 |
| Propagation Delay (tPD) | — | 25 ns |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 5 V (TTL-compatible) |
| Operating Mode | — | Turbo-only (no slow-power mode) |
| Package Code | — | LC = 68-pin JLCC |
| Tipe Mounting | — | Surface Mount |
| Programmable Interconnect | — | Global + Local buses |
| Programming Method | — | Altera Classic programmer + MAX+PLUS II legacy flow |
| Status Lingkungan Hidup | — | Obsolete (legacy Altera Classic family) |