EP1810LC-30 vs EP1810LC-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-30 sa pamamagitan ng Altera at EP1810LC-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810LC-30 EP1810LC-25
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD —
Macrocells 48 48
Flip-Flops 48 (one per macrocell) —
Speed Grade (tPD) 30 ns —
Volte ng Pagbibigay 5 V (typical) —
Technology CMOS, low-power (LC) CMOS EPLD (erasable programmable logic device)
Packhaging JLCC-68 (68-pin J-Lead ceramic chip carrier) 68-pin JLCC (J-leaded ceramic chip carrier)
Programming Device programmer or JTAG —
Temperature na Operasyon [DATA_NEEDED: temperature grade] [DATA_NEEDED: temperature grade for LC package]
Standby Current [DATA_NEEDED: ICC standby] —
Bilang ng Pins 68 —
Number of I/O Pins [DATA_NEEDED: I/O count] —
Logic Blocks 48 macrocells —
Tindminan RoHS unknown (legacy ceramic package) [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet]
Product Family — Altera Classic EPLD
Part Number — EP1810LC-25
Propagation Delay (tPD) — 25 ns
Dedicated Inputs — 12
I/O Pins — 48
External Clock Inputs — 4
Supply Voltage (VCC) — 5 V (TTL-compatible)
Operating Mode — Turbo-only (no slow-power mode)
Package Code — LC = 68-pin JLCC
Uri ng Pagpapasok — Surface Mount
Programmable Interconnect — Global + Local buses
Programming Method — Altera Classic programmer + MAX+PLUS II legacy flow
Katayuan ng Lifecycle — Obsolete (legacy Altera Classic family)

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