EPM570T144C3 - MAX II CPLD 440 LE 5.4ns TQFP-144 | Intel
MPN: EPM570T144C3 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $51.99 | $51.99 |
| 10 | $47.5 | $475.00 |
| 100 | $38.25 | $3,825.00 |
| 500 | $31.9 | $15,950.00 |
| 1,000 | $27.4 | $27,400.00 |
Drop-in alternatives for EPM570T144C3 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM570T144C3N
β Drop-Inβ In Stock
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View Datasheet βEPM570T144C4N
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View Datasheet βEPM570T144C5N
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View Datasheet βEPM570GT144C3
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
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View Datasheet βEPM570F256C3
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
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View Datasheet βEPM570T144C3 Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Device | EPM570 |
| Logic Elements (LEs) | 440 |
| Macro Cells | 440 |
| Maximum User I/O Pins | 160 |
| User Flash Memory | 4.0 Kbits |
| Logic Array Blocks (LABs) | 8 |
| Speed Grade | C3 (5.4 ns tPD1) |
| Process Technology | 0.18 Β΅m |
| Core Voltage (VCCINT) | 3.3 V (internal regulator generates 2.5 V core) |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) |
| Maximum Frequency (internal) | 304 MHz |
| Propagation Delay (tPD1) | 5.4 ns |
| Package | 144-pin TQFP (20 mm Γ 20 mm Γ 1.4 mm) |
| Operating Temperature (Commercial) | 0 Β°C to +85 Β°C |
| Programming Interface | IEEE 1149.1 JTAG (ISP) |
| Configuration | Non-volatile, instant-on (single-chip) |
EPM570T144C3 Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | I/O β User I/O pin (bank 1) |
| Pin 12 | I/O β User I/O pin (bank 1) |
| Pin 13 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 14 | I/O β User I/O pin (bank 1) |
| Pin 15 | I/O β User I/O pin (bank 1) |
| Pin 16 | I/O β User I/O pin (bank 1) |
| Pin 17 | I/O β User I/O pin (bank 1) |
| Pin 18 | I/O β User I/O pin (bank 1) |
| Pin 19 | I/O β User I/O pin (bank 1) |
| Pin 20 | I/O β User I/O pin (bank 1) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O pin (bank 2) |
| Pin 23 | I/O β User I/O pin (bank 2) |
| Pin 24 | I/O β User I/O pin (bank 2) |
| Pin 25 | I/O β User I/O pin (bank 2) |
| Pin 26 | I/O β User I/O pin (bank 2) |
| Pin 27 | I/O β User I/O pin (bank 2) |
| Pin 28 | I/O β User I/O pin (bank 2) |
| Pin 29 | I/O β User I/O pin (bank 2) |
| Pin 30 | I/O β User I/O pin (bank 2) |
| Pin 31 | I/O β User I/O pin (bank 2) |
| Pin 32 | I/O β User I/O pin (bank 2) |
| Pin 33 | I/O β User I/O pin (bank 2) |
| Pin 34 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 35 | I/O β User I/O pin (bank 2) |
| Pin 36 | I/O β User I/O pin (bank 2) |
| Pin 37 | I/O β User I/O pin (bank 2) |
| Pin 38 | I/O β User I/O pin (bank 2) |
| Pin 39 | I/O β User I/O pin (bank 2) |
| Pin 40 | I/O β User I/O pin (bank 2) |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O pin (bank 3) |
| Pin 43 | I/O β User I/O pin (bank 3) |
| Pin 44 | I/O β User I/O pin (bank 3) |
| Pin 45 | I/O β User I/O pin (bank 3) |
| Pin 46 | I/O β User I/O pin (bank 3) |
| Pin 47 | I/O β User I/O pin (bank 3) |
| Pin 48 | I/O β User I/O pin (bank 3) |
| Pin 49 | I/O β User I/O pin (bank 3) |
| Pin 50 | I/O β User I/O pin (bank 3) |
| Pin 51 | I/O β User I/O pin (bank 3) |
| Pin 52 | I/O β User I/O pin (bank 3) |
| Pin 53 | I/O β User I/O pin (bank 3) |
| Pin 54 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 55 | I/O β User I/O pin (bank 3) |
| Pin 56 | I/O β User I/O pin (bank 3) |
| Pin 57 | I/O β User I/O pin (bank 3) |
| Pin 58 | I/O β User I/O pin (bank 3) |
| Pin 59 | I/O β User I/O pin (bank 3) |
| Pin 60 | I/O β User I/O pin (bank 3) |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O pin (bank 4) |
| Pin 63 | I/O β User I/O pin (bank 4) |
| Pin 64 | I/O β User I/O pin (bank 4) |
| Pin 65 | I/O β User I/O pin (bank 4) |
| Pin 66 | I/O β User I/O pin (bank 4) |
| Pin 67 | I/O β User I/O pin (bank 4) |
| Pin 68 | I/O β User I/O pin (bank 4) |
| Pin 69 | I/O β User I/O pin (bank 4) |
| Pin 70 | I/O β User I/O pin (bank 4) |
| Pin 71 | I/O β User I/O pin (bank 4) |
| Pin 72 | I/O β User I/O pin (bank 4) |
| Pin 73 | I/O β User I/O pin (bank 4) |
| Pin 74 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 75 | I/O β User I/O pin (bank 4) |
| Pin 76 | I/O β User I/O pin (bank 4) |
| Pin 77 | I/O β User I/O pin (bank 4) |
| Pin 78 | I/O β User I/O pin (bank 4) |
| Pin 79 | I/O β User I/O pin (bank 4) |
| Pin 80 | I/O β User I/O pin (bank 4) |
| Pin 81 | GND β Ground |
| Pin 82 | I/O β User I/O pin (bank 1) |
| Pin 83 | I/O β User I/O pin (bank 1) |
| Pin 84 | I/O β User I/O pin (bank 1) |
| Pin 85 | I/O β User I/O pin (bank 1) |
| Pin 86 | I/O β User I/O pin (bank 1) |
| Pin 87 | I/O β User I/O pin (bank 1) |
| Pin 88 | I/O β User I/O pin (bank 1) |
| Pin 89 | I/O β User I/O pin (bank 1) |
| Pin 90 | I/O β User I/O pin (bank 1) |
| Pin 91 | I/O β User I/O pin (bank 1) |
| Pin 92 | I/O β User I/O pin (bank 1) |
| Pin 93 | VCCINT β Internal core voltage (3.3 V, internal regulator generates 2.5 V core) |
| Pin 94 | I/O β User I/O pin (bank 1) |
| Pin 95 | I/O β User I/O pin (bank 1) |
| Pin 96 | I/O β User I/O pin (bank 1) |
| Pin 97 | I/O β User I/O pin (bank 1) |
| Pin 98 | I/O β User I/O pin (bank 1) |
| Pin 99 | I/O β User I/O pin (bank 1) |
| Pin 100 | I/O β User I/O pin (bank 1) |
| Pin 101 | GND β Ground |
| Pin 102 | I/O β User I/O pin (bank 2) |
| Pin 103 | I/O β User I/O pin (bank 2) |
| Pin 104 | I/O β User I/O pin (bank 2) |
| Pin 105 | I/O β User I/O pin (bank 2) |
| Pin 106 | I/O β User I/O pin (bank 2) |
| Pin 107 | I/O β User I/O pin (bank 2) |
| Pin 108 | I/O β User I/O pin (bank 2) |
| Pin 109 | I/O β User I/O pin (bank 2) |
| Pin 110 | I/O β User I/O pin (bank 2) |
| Pin 111 | I/O β User I/O pin (bank 2) |
| Pin 112 | I/O β User I/O pin (bank 2) |
| Pin 113 | I/O β User I/O pin (bank 2) |
| Pin 114 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 115 | I/O β User I/O pin (bank 2) |
| Pin 116 | I/O β User I/O pin (bank 2) |
| Pin 117 | I/O β User I/O pin (bank 2) |
| Pin 118 | I/O β User I/O pin (bank 2) |
| Pin 119 | I/O β User I/O pin (bank 2) |
| Pin 120 | I/O β User I/O pin (bank 2) |
| Pin 121 | GND β Ground |
| Pin 122 | TMS β JTAG Test Mode Select |
| Pin 123 | TDI β JTAG Test Data In |
| Pin 124 | TCK β JTAG Test Clock |
| Pin 125 | I/O β User I/O pin (bank 4) |
| Pin 126 | I/O β User I/O pin (bank 4) |
| Pin 127 | I/O β User I/O pin (bank 4) |
| Pin 128 | I/O β User I/O pin (bank 4) |
| Pin 129 | I/O β User I/O pin (bank 4) |
| Pin 130 | I/O β User I/O pin (bank 4) |
| Pin 131 | I/O β User I/O pin (bank 4) |
| Pin 132 | I/O β User I/O pin (bank 4) |
| Pin 133 | I/O β User I/O pin (bank 4) |
| Pin 134 | I/O β User I/O pin (bank 4) |
| Pin 135 | I/O β User I/O pin (bank 4) |
| Pin 136 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 137 | I/O β User I/O pin (bank 4) |
| Pin 138 | I/O β User I/O pin (bank 4) |
| Pin 139 | I/O β User I/O pin (bank 4) |
| Pin 140 | I/O β User I/O pin (bank 4) |
| Pin 141 | TDO β JTAG Test Data Out |
| Pin 142 | I/O β User I/O pin (bank 4) |
| Pin 143 | I/O β User I/O pin (bank 4) |
| Pin 144 | I/O β User I/O pin (bank 4) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570T144C3 is suitable for 7 applications: Bus Interface Bridging, Power-Up Sequencing Controller, Address Decoding and Chip-Select Generation, Industrial Control and Motor-Drive Front-End Logic, LED Display Driver and Multiplexing, Legacy TTL/CMOS Glue Logic Replacement, I/O Expansion for Microcontrollers.
Bus Interface Bridging
The EPM570T144C3 is well suited to bus-bridging tasks where a microprocessor must connect to peripherals with mismatched bus widths or voltages. Its 5.4 ns tPD1 propagation delay comfortably handles asynchronous 8/16/32-bit handshakes up to ~50 MHz, and its MultiVolt I/O supports direct 1.5 V, 1.8 V, 2.5 V, and 3.3 V signaling without level shifters. With 160 user I/O available in the TQFP-144, designers can implement full 32-bit address/data muxing plus control signal glue in a single device.
Recommended
Power-Up Sequencing Controller
Power-up sequencers require deterministic timing and instant-on behavior - exactly the strengths of the EPM570T144C3. Because the device is non-volatile, it begins executing its state machine within microseconds of VCCINT reaching regulation, well before most analog rails stabilize. Its 440 LE are more than sufficient to implement multi-rail PG (power-good) chains with programmable delays using internal logic and a JTAG-updatable delay parameter. Compared with discrete RC sequencing networks, the CPLD approach enables in-system re-tuning without board rework.
Recommended
Address Decoding and Chip-Select Generation
The EPM570T144C3 is a classic choice for address decoding in microcontroller and microprocessor systems where multiple peripherals share a bus. Its 5.4 ns tPD1 propagation delay introduces minimal wait-state insertion, and its 160 user I/O accommodate the wide address ranges typical of 32-bit cores. Designers can implement any decoding logic - full binary, partial, or windowed - and update it via JTAG ISP without re-spinning the board, dramatically shortening prototype iterations.
Recommended
Industrial Control and Motor-Drive Front-End Logic
Industrial control panels often require deterministic glue logic for sensor conditioning, fault aggregation, and drive enable signals. The EPM570T144C3 supports up to 160 I/O, enabling direct interface to 24 V opto-isolated inputs and 3.3 V logic outputs via MultiVolt banks. Its instant-on non-volatile configuration prevents inrush misbehavior on cold-boot, and its 5.4 ns tPD1 timing supports deterministic fault-interlock response. For extended temperature ranges, the I-grade EPM570T144I3 variant is preferred where available in the same footprint.
Recommended
LED Display Driver and Multiplexing
The EPM570T144C3 can drive LED matrix displays by multiplexing rows and columns with precise timing. Its 304 MHz maximum internal frequency and 5.4 ns tPD1 allow high-refresh-rate PWM generation for color-mixing or large dot-matrix panels. With 160 user I/O, the device can directly sink 16+ row/column lines per panel without external drivers, and the JTAG ISP allows firmware-updates for new display patterns without re-soldering.
Recommended
Legacy TTL/CMOS Glue Logic Replacement
Designers often replace dozens of discrete 74-series TTL or 4000-series CMOS packages with a single EPM570T144C3, simplifying the BOM and reducing PCB area. The 440 LE are sufficient to implement encoders, decoders, multiplexers, latches, and small state machines that previously occupied a board corner. Because the configuration is non-volatile and field-updatable via JTAG, design bugs found in production can be patched without reworking the PCB.
Recommended
I/O Expansion for Microcontrollers
When a microcontroller runs out of GPIO, the EPM570T144C3 can add up to 160 individually configurable I/O lines through a simple SPI or parallel interface. Each pin supports MultiVolt signaling, allowing the CPLD to talk to 1.8 V sensors and 3.3 V MCUs from a single device. The 5.4 ns tPD1 timing keeps I/O skew well under one SPI clock period, and the JTAG interface enables runtime I/O test and reconfiguration for safety-critical applications.
Recommended
Recommended Products Summary
Engineering reference data for EPM570T144C3 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570T144C3N | EPM570T144C4N | EPM570T144C5N | EPM570GT144C3 | EPM570F256C3 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 compatible (FineLine BGA migration) |
| Speed Grade | C3 (5.4 ns tPD1) | C3 (5.4 ns) | C4 (~6.5 ns) | C5 (~8.0 ns) | C3 (5.4 ns) | C3 (5.4 ns) |
| Logic Elements | 440 | 440 | 440 | 440 | 440 | 440 |
| User I/O Pins (max) | 160 | 160 | 160 | 160 | 160 | 160 |
| Operating Temperature | 0 C to +85 C (Commercial) | 0 C to +85 C | 0 C to +85 C | 0 C to +85 C | 0 C to +85 C | 0 C to +85 C |
| Lead-Free / RoHS | Unknown | Yes (Pb-free) | Yes (Pb-free) | Yes (Pb-free) | Yes (Pb-free, legacy G-suffix) | Depends on sub-suffix (N) |
| Approx. Unit Price (USD, as of 2026-09-12) | 51.99 | 53.00 | 49.00 | 45.00 | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Instant-on non-volatile configuration eliminates external boot PROM (vs EPM570F256C3 (FineLine BGA migration option))
- 160 user I/O pins in a 0.5 mm pitch TQFP - highest count in MAX II family for this package (vs EPM240T100C3 (TQFP-100))
- MultiVolt I/O supports 1.5 V, 1.8 V, 2.5 V, and 3.3 V in a single device (vs Discrete 74-series TTL glue logic)
Design Notes
The EPM570T144C3 requires a 3.3 V supply on VCCINT (an internal LDO generates the 2.5 V core), and each of the four I/O banks (VCCIO1-4) may be powered independently at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. Place one 0.1 Β΅F decoupling capacitor within 2 mm of every VCCINT and VCCIO pin, plus a single 10 Β΅F bulk capacitor per bank to suppress switching transients during ISP programming. Avoid powering VCCIO at a voltage not supported by the chosen I/O standard.
The 144-pin TQFP package has a 0.5 mm pitch and 20 mm Γ 20 mm body, which demands careful trace escape routing. Use 0.15 mm/0.20 mm trace/space between TQFP fingers and fan out to inner power planes on the second layer. Keep all four I/O bank supplies (VCCIO1-4) on a single plane region if possible, and provide at least one continuous GND plane beneath the device for return-path integrity during JTAG boundary-scan.
Pin 1 is located at the top-left of the TQFP-144 package when the dot marker is oriented to the upper-left. The JTAG signals TCK (pin 124), TMS (pin 122), TDI (pin 123), and TDO (pin 141) must be routed away from high-frequency switching signals and length-matched within 25 mm to avoid boundary-scan failures. A 10 kΞ© pull-up on TDI and TMS, plus a 10 kΞ© pull-up on TDO, is recommended for stable JTAG operation.
Do not confuse the speed-grade suffix C3 (fastest, 5.4 ns) with C5 (slowest, ~8.0 ns) when substituting across production runs - timing closure may fail. The 'T' prefix in EPM570T144 indicates TQFP package, while 'G' and 'F' prefixes denote legacy lead-free and FineLine BGA migration options. Always re-validate the Quartus II fitter report after a speed-grade or package-marker change.
Although CPLD outputs have slower edge rates than FPGAs (typically 2-3 ns), the 5.4 ns tPD1 timing budget assumes a 50 pF load. For high-fanout signals driving more than eight inputs or external cables, add a series 22 Ξ© damping resistor close to the CPLD output to limit overshoot and ringing. For MultiVolt I/O banks, mix only compatible voltage standards in the same bank - mixing 1.5 V and 3.3 V in one bank is not allowed.
Compliance Information
RoHS/lead-free status was not confirmed in the verified web data; the EPM570T144C3N variant is documented as Pb-free. AEC-Q100 is not applicable to a general-purpose commercial CPLD. Conflict-minerals statement available from Intel's Corporate Responsibility Report.
